DP83848I-MAU-EK National Semiconductor, DP83848I-MAU-EK Datasheet
DP83848I-MAU-EK
Specifications of DP83848I-MAU-EK
Related parts for DP83848I-MAU-EK
DP83848I-MAU-EK Summary of contents
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... The DP83848I features integrated sublayers to sup- port both 10BASE-T and 100BASE-TX Ethernet proto- cols, which ensures compatibility and interoperability with all other standards based Ethernet solutions. The DP83848I is offered in a small form factor (48 pin LQFP) so that a minimum of board space is needed. Applications • High End Peripheral Devices • ...
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... Transmit Block DAC Boundary Auto-MDIX Scan JTAG www.national.com MII/RMII/SNI SERIAL MANAGEMENT MII/RMII/SNI INTERFACES MII Registers Auto-Negotiation State Machine Clock Generation TD± RD± REFERENCE CLOCK Figure 1. DP83848I Functional Block Diagram 2 RX_CLK RX_DATA 10BASE-T & 100BASE-TX Receive Block ADC LED Drivers LEDS ...
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Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Mb/s MII Transmit Timing 8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Figure 1. DP83848I Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 6. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . . 28 Figure 9 ...
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Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Pin Layout PFBIN2 RX_CLK RX_DV/MII_MODE CRS/CRS_DV/LED_CFG RX_ER/MDIX_EN COL/PHYAD0 RXD_0/PHYAD1 RXD_1/PHYAD2 RXD_2/PHYAD3 RXD_3/PHYAD4 IOGND IOVDD33 www.national.com DP83848I Top View NS Package Number VBH48A 8 RBIAS 24 PFBOUT 23 AVDD33 22 RESERVED 21 RESERVED 20 AGND 19 PFBIN1 AGND ...
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... TXD_1 TXD_2 TXD_3 Note: Strapping pin option. Please see Section 1.7 for strap definitions. All DP83848I signal pins are I/O cells regardless of the par- ticular use. The definitions below define the functionality of the I/O cells for each pin. Type: I Input Type: O ...
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Signal Name Type RX_CLK O RX_DV RX_ER RXD_0 RXD_1 RXD_2 RXD_3 CRS/CRS_DV COL www.national.com Pin # Description 38 MII RECEIVE CLOCK: Provides the 25 MHz ...
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... Pin # Description 34 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848I and must be connected MHz 0.005% (+50 ppm) clock source. The DP83848I supports ei- ther an external crystal resonator connected across pins X1 and X2 external CMOS-level oscillator source connected to pin X1 only. RMII REFERENCE CLOCK: This pin is the primary clock refer- ence input for the RMII mode and must be connected MHz 0 ...
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... Description 29 RESET: Active Low input that initializes or re-initializes the DP83848I. Asserting this pin low for at least 1 s will force a reset process to occur. All internal registers will re-initialize to their de- fault states as specified for each bit in the Register Block section. All strap options are re-initialized as well. ...
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... GND ( (1) through 2.2 k resistors. These pins should CC NEVER be connected directly to GND or VCC. The value set at this input is latched into the DP83848I at Hard- ware-Reset. The float/pull-down status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. ...
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Mb/s and 100 Mb/s PMD Interface Signal Name Type TD-, TD+ I/O RD-, RD+ I/O 1.9 Special Connections Signal Name Type RBIAS PFBOUT O PFBIN1 PFBIN2 RESERVED I/O 1.10 Power Supply Pins Signal Name IOVDD33 IOGND DGND AVDD33 ...
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Package Pin Assignments VBH48A Pin # Pin Name 1 TX_CLK 2 TX_EN 3 TXD_0 4 TXD_1 5 TXD_2 6 TXD_3/SNI_MODE 7 PWR_DOWN/INT 8 TCK 9 TDO 10 TMS 11 TRST# 12 TDI ...
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... Auto-Negotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83848I (only the 100BASE-T4 bit is not set since the DP83848I does not support that function). The BMSR also provides status on: — ...
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... FLP (Fast Link Pulse) bursts. 2.1.5 Enabling Auto-Negotiation via Software It is important to note that if the DP83848I has been initial- ized upon power- non-auto-negotiating device (forced technology), and it is then required that Auto-Nego- tiation or re-Auto-Negotiation be initiated via software, ...
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... PHYAD3 46 PHYAD4 The DP83848I can be set to respond to any of 32 possible PHY addresses via strap pins. The information is latched into the PHYCR register (address 19h, bits [4:0]) at device power-up and hardware reset. The PHY Address pins are shared with the RXD and COL pins. Each DP83848I or port sharing an MDIO bus in a system must have a unique physical address ...
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... LED Interface The DP83848I supports three configurable Light Emitting Diode (LED) pins. The device supports three LED configu- rations: Link, Speed, Activity and Collision. Function are Mode LED_CFG[1] LED_CFG[0] (bit 6) (bit 5) or (pin40) 1 don’t care The LED_LINK pin in Mode 1 indicates the link status of the port ...
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... Mb/s). www.national.com 2.6 Internal Loopback The DP83848I includes a Loopback Test mode for facilitat- ing system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Reg- ister (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs ...
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... Collisions are reported by the COL signal on the MII. If the DP83848I is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network ...
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... IDLE and turnaround, will pull MDIO high. In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83848I with a sequence that can be used to establish synchronization. This preamble may be gener- ated either by driving MDIO high for 32 consecutive MDC ...
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... MDIO in conjunction with a continuous MDC, or the management access made to determine whether Pre- amble Suppression is supported. While the DP83848I requires an initial preamble sequence of 32 bits for management initialization, it does not require a full 32-bit sequence between each subsequent transac- tion. A minimum of one idle bit between management transactions is required as specified in the IEEE 802 ...
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... Binary to MLT-3 converter / Common Driver The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for applications where data conversion is not always required. The DP83848I implements the 100BASE-TX transmit state machine diagram as specified in the IEEE 802.3u Stan- dard, Clause 24. TX_CLK ...
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Table 5. 4B5B CCode-group Encoding and Injection DATA CODES IDLE AND CONTROL CODES INVALID CODES ...
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... NRZ data from the code-group encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83848I uses the PHY_ID (pins PHYAD [4:0]) to set a unique seed value. 4.1.2 NRZ to NRZI Encoder After the transmit data stream has been serialized and ...
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RX_DV/CRS RX_CLK RX_DATA VALID SSD DETECT Figure 7. 100BASE-TX Receive Block Diagram RXD[3:0] / RX_ER 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT DESCRAMBLER NRZI TO NRZ DECODER MLT-3 TO BINARY DECODER DIGITAL SIGNAL PROCESSOR ANALOG FRONT END RD 27 ...
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... Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, www.national.com tive to ensure proper conditioning of the received signal independent of the cable length. The DP83848I utilizes an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’ The Digital Equalizer removes ISI (inter symbol interfer- ence) from the receive data stream by continuously adapt- ing to provide a filter with the inverse frequency response of the channel ...
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... Standard for both voltage thresholds and timing parame- ters. Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u Auto-Negotiation by the 100BASE-TX receiver do not cause the DP83848I to assert signal detect. 4.2.4 MLT-3 to NRZI Decoder The DP83848I decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data ...
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... In Half Duplex mode the DP83848I functions as a standard IEEE 802.3 CSMA/CD protocol. Full Duplex Mode In Full Duplex mode the DP83848I is capable of simulta- neously transmitting and receiving without asserting the collision signal. The DP83848I's 10 Mb/s ENDEC is designed to encode and decode simultaneously. 30 10BASE-T ...
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... Smart Squelch The smart squelch is responsible for determining when valid data is present on the differential receive inputs. The DP83848I implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode. ...
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... Transmit and Receive Filtering External 10BASE-T filters are not required when using the DP83848I, as the required signal conditioning is integrated into the device. Only isolation transformers and impedance matching resis- tors are required for the 10BASE-T transmit and receive interface ...
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Design Guidelines 5.1 TPI Network Circuit Figure 11 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. To the right is a partial list of recommended transformers important that the user realize that variations with ...
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... After the system is assembled, internal compo- nents are less sensitive from ESD events. See Section 8.0 for ESD rating. 5.3 Clock In (X1) Requirements The DP83848I supports an external CMOS level oscillator source or a crystal resonator device. Oscillator If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating ...
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... Frequency Stability Load Capacitance 25 5.4 Power Feedback Circuit To ensure correct operation for the DP83848I, parallel caps with values (Tantalum) and 0.1 placed close to pin 23 (PFBOUT) of the device. Pin 18 (PFBIN1) and pin 37 (PFBIN2) must be connected to pin 23 (PFBOUT), each pin requires a small capacitor ( ...
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... Energy Detect Mode When Energy Detect is enabled and there is no activity on the cable, the DP83848I will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83848I to go through a normal power up sequence. Regardless of cable activity, the DP83848I will occasionally wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible ...
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... Reset Operation The DP83848I includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal opera- tion, the device can be reset by a hardware or software reset. 6.1 Hardware Reset A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 RESET_N ...
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Register Block Offset Access Hex Decimal 00h 0 RW 01h 1 RO 02h 2 RO 03h 3 RO 04h 4 RW 05h 5 RW 05h 5 RW 06h 6 RW 07h 7 RW 08h-Fh 8-15 RW 10h 16 RO ...
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Register Definition In the register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access SC — =Register sets on event occurrence and Self-Clears when event ends — RW/SC =Read Write access/Self Clearing bit — ...
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Basic Mode Control Register (BMCR) Table 12. Basic Mode Control Register (BMCR), address 0x00 Bit Bit Name 15 Reset 14 Loopback 13 Speed Selection 12 Auto-Negotiation Enable 11 Power Down 10 Isolate 9 Restart Auto- Negotiation 8 Duplex Mode ...
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Table 12. Basic Mode Control Register (BMCR), address 0x00 (Continued) Bit Bit Name Default 7 Collision Test 0, RW 6:0 RESERVED 0, RO Description Collision Test Collision test enabled Normal operation. When set, this bit will ...
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Basic Mode Status Register (BMSR) Table 13. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name 15 100BASE-T4 14 100BASE-TX Full Duplex 13 100BASE-TX Half Duplex 12 10BASE-T Full Duplex 11 10BASE-T Half Duplex 10:7 RESERVED 6 MF ...
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... The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848I. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num- ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management ...
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Table 16. Negotiation Advertisement Register (ANAR), address 0x04 (Continued) Bit Bit Name 11 ASM_DIR 10 PAUSE TX_FD 10_FD 5 10 4:0 Selector www.national.com Default 0, RW Asymmetric PAUSE Support for Full Duplex Links: The ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 17. Auto-Negotiation Link Partner Ability ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 18. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 Bit Bit Name ACK ACK2 11 Toggle 10:0 CODE <000 0000 0000>, 7.1.8 ...
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Table 19. Auto-Negotiate Expansion Register (ANER), address 0x06 (Continued) Bit Bit Name 0 LP_AN_ABLE 7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 20. ...
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Extended Registers 7.2.1 PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. Table 21. PHY Status Register (PHYSTS), address 0x10 Bit Bit Name 15 RESERVED 14 MDI-X ...
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Table 21. PHY Status Register (PHYSTS), address 0x10 (Continued) Bit Bit Name Default 5 Jabber Detect Auto-Neg Complete Loopback Status Duplex Status Speed Status Link ...
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MII Interrupt Control Register (MICR) This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, any of the counters becoming half-full. The individual interrupt events must be ...
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MII Interrupt Status and Misc. Control Register (MISR) This register contains event status and enables for the interrupt function event has occurred since the last read of this register, the corresponding status bit will be set. If ...
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False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 24. False Carrier Sense Counter Register (FCSCR), ...
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Mb/s PCS Configuration and Status Register (PCSR) Table 26. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 Bit Bit Name 15:13 RESERVED 12 RESERVED 11 RESERVED 10 TQ_EN 9 SD FORCE PMA 8 SD_OPTION 7 DESC_TIME ...
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RMII and Bypass Register (RBR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 27. RMII and Bypass Register (RBR), addresses 0x17 Bit Bit Name 15:6 RESERVED 5 RMII_MODE ...
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PHY Control Register (PHYCR) Table 29. PHY Control Register (PHYCR), address 0x19 Bit Bit Name 15 MDIX_EN 14 FORCE_MDIX 13 PAUSE_RX 12 PAUSE_TX 11 BIST_FE 10 PSR_15 9 BIST_STATUS 8 BIST_START 7 BP_STRETCH Default Strap, RW Auto-MDIX Enable: 1 ...
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Table 29. PHY Control Register (PHYCR), address 0x19 (Continued) Bit Bit Name 6 LED_CNFG[1] 5 LED_CNFG[0] 4:0 PHYADDR[4:0] 7.2.10 10Base-T Status/Control Register (10BTSCR) Table 30. 10Base-T Status/Control Register (10BTSCR), address 0x1A Bit Bit Name 15 10BT_SERIAL 14:12 RESERVED 11:9 SQUELCH ...
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Table 30. 10Base-T Status/Control Register (10BTSCR), address 0x1A Bit Bit Name Default 7 LP_DIS FORCE_LINK_10 RESERVED POLARITY RO/LH 3 RESERVED RESERVED HEARTBEAT_DIS ...
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CD Test and BIST Extensions Register (CDCTRL1) Table 31. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B Bit Bit Name 15:8 BIST_ERROR_CO UNT 7:6 RESERVED 5 BIST_CONT_MOD E 4 CDPATTEN_10 3 RESERVED 2 10MEG_PATT_GA P 1:0 CDPATTSEL[1:0] www.national.com ...
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Energy Detect Control (EDCR) Table 32. Energy Detect Control (EDCR), address 0x1D Bit Bit Name 15 ED_EN 14 ED_AUTO_UP 13 ED_AUTO_DOWN 12 ED_MAN 11 ED_BURST_DIS 10 ED_PWR_STATE 9 ED_ERR_MET 8 ED_DATA_MET 7:4 ED_ERR_COUNT 3:0 ED_DATA_COUNT Default 0, RW Energy ...
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Electrical Specifications Note: All parameters are guaranteed by test, statistical analysis or design. Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature (T ) STG Max ...
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Symbol Pin Types Parameter V PMD Output 100M Transmit TPTD_100 Pair Voltage V PMD Output 100M Transmit TPTDsym Pair Voltage Symmetry V PMD Output 10M Transmit TPTD_10 Pair Voltage C I CMOS Input IN1 Capacitance C O CMOS Output OUT1 ...
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AC Specs 8.2.1 Power Up Timing Vcc X1 clock Hardware RESET_N MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T2.1.1 Post Power Up Stabilization time prior to MDC preamble for register accesses ...
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Reset Timing Vcc X1 clock Hardware RESET_N MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T2.2.1 Post RESET Stabilization time prior to MDC preamble for reg- ister accesses T2.2.2 Hardware Configuration Latch- ...
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MII Serial Management Timing MDC MDIO (output) MDC MDIO (input) Parameter Description T2.3.1 MDC to MDIO (Output) Delay Time T2.3.2 MDIO (Input) to MDC Setup Time T2.3.3 MDIO (Input) to MDC Hold Time T2.3.4 MDC Frequency 8.2.4 100 Mb/s ...
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Mb/s MII Receive Timing RX_CLK T2.5.2 RXD[3:0] RX_DV RX_ER Parameter Description T2.5.1 RX_CLK High/Low Time T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode Note: RX_CLK may be held low or high for a longer period ...
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Transmit Packet Deassertion Timing TX_CLK TX_EN TXD PMD Output Pair Parameter Description T2.7.1 TX_CLK to PMD Output Pair Deassertion Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deasser- ...
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Transmit Timing (t +1 rise PMD Output Pair T2.8.2 PMD Output Pair eye pattern Parameter Description T2.8.1 100 Mb/s PMD Output Pair t and t F 100 Mb/s t and t Mismatch R F T2.8.2 100 Mb/s PMD ...
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Receive Packet Latency Timing PMD Input Pair IDLE T2.9.1 CRS RXD[3:0] RX_DV RX_ER Parameter Description T2.9.1 Carrier Sense ON Delay T2.9.2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the first ...
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Mb/s MII Transmit Timing T2.11.1 TX_CLK TXD[3:0] TX_EN Parameter Description T2.11.1 TX_CLK High/Low Time T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise Note: An attached Mac should drive the transmit ...
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Mb/s Serial Mode Transmit Timing TX_CLK TXD[0] TX_EN Parameter Description T2.13.1 TX_CLK High Time T2.13.2 TX_CLK Low Time T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 8.2.14 10 Mb/s Serial ...
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Transmit Timing (Start of Packet) TX_CLK TX_EN TXD PMD Output Pair Parameter Description T2.15.1 Transmit Output Delay from the Falling Edge of TX_CLK T2.15.2 Transmit Output Delay from the Rising Edge of TX_CLK Note: 1 bit time = ...
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Receive Timing (Start of Packet TPRD T2.17.1 CRS RX_CLK T2.17.2 RX_DV 0000 RXD[3:0] Parameter Description T2.17.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) T2.17.2 RX_DV Latency T2.17.3 Receive Data Latency Note: 10BASE-T ...
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Mb/s Heartbeat Timing TX_EN TX_CLK COL Parameter Description T2.19.1 CD Heartbeat Delay T2.19.2 CD Heartbeat Duration 8.2.20 10 Mb/s Jabber Timing TXE PMD Output Pair COL Parameter Description T2.20.1 Jabber Activation Time T2.20.2 Jabber Deactivation Time T2.19.2 T2.19.1 ...
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Normal Link Pulse Timing Normal Link Pulse(s) Parameter Description T2.21.1 Pulse Width T2.21.2 Pulse Period Note: These specifications represent transmit timings. 8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing T2.22.1 Fast Link Pulse(s) Parameter Description T2.22.1 Clock, Data Pulse ...
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Signal Detect Timing PMD Input Pair T2.23.1 SD+ internal Parameter Description T2.23.1 SD Internal Turn-on Time T2.23.2 SD Internal Turn-off Time Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. 8.2.24 100 Mb/s Internal Loopback ...
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Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] Parameter Description T2.25.1 TX_EN to RX_DV Loopback Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. www.national.com T2.25.1 Notes 10 Mb/s ...
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RMII Transmit Timing X1 TXD[1:0] TX_EN PMD Output Pair Parameter Description T2.26.1 X1 Clock Period T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising T2.26.4 X1 Clock to PMD Output Pair Latency ...
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RMII Receive Timing IDLE (J/K) PMD Input Pair X1 T2.27.3 RX_DV CRS_DV RXD[1:0] RX_ER Parameter Description T2.27.1 X1 Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising T2.27.3 CRS ON delay T2.27.4 CRS OFF delay ...
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Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) H/W or S/W Reset (with PHYAD = 00000) MODE Parameter Description T2.28.1 From software clear of bit 10 in the BMCR register to the transi- ...
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Mb TX_CLK Timing X1 TX_CLK Parameter Description T2.30 TX_CLK delay Note TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data. www.national.com ...
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Notes: 83 www.national.com ...
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