SI3215PPQX-EVB Silicon Laboratories Inc, SI3215PPQX-EVB Datasheet
SI3215PPQX-EVB
Specifications of SI3215PPQX-EVB
Related parts for SI3215PPQX-EVB
SI3215PPQX-EVB Summary of contents
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P SLIC Features Performs all BORSCHT functions Software-programmable internal balanced ...
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Si3215 2 Rev. 0.92 ...
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Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . ...
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Si3215 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage 2 Operating Temperature Range Storage Temperature Range TSSOP-38 Thermal Resistance, Typical QFN-38 Thermal Resistance, Typical 2 ...
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Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3215 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply ...
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Si3215 Table 3. AC Characteristics (Continued 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter 2-Wire Return Loss Transhybrid Balance 4 Idle Channel ...
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Figure 1. Transmit and Receive Path SNDR Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 2. Overload Compression Performance Rev. 0.92 Si3215 Acceptable ...
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Si3215 Figure 3. Transmit Path Frequency Response 8 Typical Response Typical Response Rev. 0.92 ...
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Figure 4. Receive Path Frequency Response Rev. 0.92 Si3215 9 ...
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Si3215 Figure 5. Transmit Group Delay Distortion 10 Figure 6. Receive Group Delay Distortion Rev. 0.92 ...
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Table 4. Linefeed Characteristics ( 3. 70°C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Loop Resistance Range R LOOP DC Loop Current Accuracy DC ...
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Si3215 Table 5. Monitor ADC Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity ...
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Table 8. Power Supply Characteristics ( 3. 5. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Power Supply Current Analog and ...
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Si3215 Table 9. Switching Characteristics—General Inputs 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width Note: ...
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SCLK t su1 CS SDI t d1 SDO Table 11. Switching Characteristics—PCM Highway Serial Interface V = 3. °C for K-Grade, – °C for B-Grade Parameter PCLK ...
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Si3215 PCLK FSYNC DRX t DTX Figure 8. PCM Highway Interface Timing Diagram 1 TIP TIP irc ...
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Table 12. Si3215/Si3215M External Component Values Component(s) C1,C2 10 µ Ceramic Low Leakage Electrolytic, ±20% C3,C4 C5,C6 C15,C16,C17,C24 C18,C19 4.7 µF Ceramic X7R, ±20% C26 C30, C31 10 µ Electrolytic, ±20% ...
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Si3215 Table 13. Si3215 BJT/Inductor DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C10 0.1 µ X7R, ±20% 1 C14 1 C25 10 µF, Electrolytic, ±20% R16 R17 1/10 W, ±5% (See AN45 R18 ...
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SDCH SDCL DCFF DCDRV Notes: 1. Values and configurations for these components can be derived from Table 20 or from “AN45: Design Guide for the Si3210 DC-DC Converter”. 2. Voltage rating for C14 and C25 must be greater than VDC. ...
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Si3215 Q1 Q4 5401 5401 R10 10 TIP Q6 5551 C8 R13 C5 220nF 5.1k 22nF Protection Circuit R6 C6 80.6 22nF RING Notes: 1. Values and configurations for these components can be derived from Table 19 or from “AN45: ...
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Table 15. Si3215/Si3215M External Component Values—Discrete Solution (Continued) Q9 NPN General Purpose BJT R1,R3 R2,R4,R5, R102,R104, R105 R6,R7 R8,R9 R10,R11 R12,R13 40.2 k Ω , 1/10 W, ± 1% R14,R26* R15 R21 1/10 W, ± 1% (See AN45 or Table ...
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Si3215 The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5, Q6. For this optional subcircuit, C7 and C8 are different in voltage and capacitance than the standard circuit. R23 and ...
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Functional Description ® The ProSLIC is a single, low-voltage CMOS device that provides all the SLIC, codec, and signal generation functions needed for a complete analog telephone interface. The ProSLIC performs overvoltage, ringing, supervision, codec, hybrid, and test (BORSCHT) ...
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Si3215 2.2.1. DC Feed Characteristics The ProSLIC has programmable constant voltage and constant current zones as depicted in Figure 14. Open circuit TIP-to-RING voltage (V ) defines the constant OC voltage zone and is programmable from 94.5 ...
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Loop Voltage and Current Monitoring The ProSLIC continuously monitors the TIP and RING voltages and external BJT currents. These values are available in registers 78–89. Table 22 lists the values that are measured and their associated registers. An internal ...
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Si3215 Table 21. ProSLIC Linefeed Operations LF[2:0]* Linefeed State 000 Open 001 Forward Active 010 Forward On-Hook Transmission 011 TIP Open 100 Ringing 101 Reverse Active 110 Reverse On-Hook Transmission 111 Ring Open *Note: The Linefeed register (LF) is located ...
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Power Monitoring and Line Fault Detection In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each external bipolar transistor. Real time output power of any one of the six linefeed transistors can be ...
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Si3215 Table 23. Associated Power Monitoring and Power Fault Registers (Continued) Power Alarm Interrupt Enable Power Alarm Automatic/Manual Detect *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped directly. ...
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Table 24. Register Set for Loop Closure Detection Parameter Register Loop Closure LCIP Interrupt Pending Loop Closure LCIE Interrupt Enable Loop Closure Threshold LCRT[5:0] Loop Closure LCRTL[5:0] Indirect ...
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Si3215 2.3.2. BJT/Inductor Circuit Option Using Si3215 The BJT/Inductor circuit option, as defined in Figure 10 on page 17, offers a flexible, low-cost solution. Depending on selected L1 inductance value and the switching frequency, the input voltage (V from 5 ...
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R , and result, the LOOP |V | voltage will also track R BAT LOOP | BAT LIM x LOOP CM OV below the ...
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Si3215 Table 26. Associated Relevant DC-DC Converter Registers Parameter DC-DC Converter Power-Off Control DC-DC Converter Calibration Enable/Status DC-DC Converter PWM Period DC-DC Converter Min. Off Time High Battery Voltage—V BATH Low Battery Voltage—V BATL V OV Note: The ProSLIC uses ...
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Clock OnE 16-Bit Cross OAT Modulo Expire Counter OIT Expire OATn OATnE OITn OITnE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Figure 18. Simplified Tone Generator Diagram 2.4.2. Oscillator ...
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Si3215 counting until the inactive timer expires. The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the OZ1 bit (direct Register 32, bit 5). This ensures ...
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O1E ... ... 0 AT1 OSS1 Tone Gen. 1 Signal Output Figure 19. Tone Generator Timing Diagram 2.4.4. Enhanced FSK Waveform Generation Enhanced FSK generation capabilities can be enabled by setting FSKEN = 1 (direct Register 108, bit ...
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Si3215 Table 28. Registers for Ringing Generation Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery ...
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Trapezoidal Ringing In addition to the sinusoidal ringing waveform, the ProSLIC supports trapezoidal illustrates a trapezoidal ringing waveform with offset V . ROFF V TIP-RING V ROFF T=1/freq t RISE Figure 20. Trapezoidal Ringing Waveform To configure the ProSLIC ...
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Si3215 β × × ( 80.6 Ω ------------ - OVR LOAD,PK β where β is the minimum expected current gain of transistors Q5 and Q6. The minimum value for V is, therefore, given by the ...
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Table 29. Associated Registers for Ring Trip Detection Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Detect Debounce Interval Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Note: The ProSLIC uses registers ...
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Si3215 40 Rev. 0.92 ...
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Receive Path In the receive path, the optionally-compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process, in which case two 8-bit words are assembled into one 16- bit word. DACG ...
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Si3215 the receive path. An additional analog loopback (ALM1) takes the digital stream at the output of the A/D converter and feeds it back to the D/A converter. (See Figure 22.) The signal path starts with the analog signal at ...
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Interrupt Logic The ProSLIC is capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected Power alarm Active timer 1 expired Inactive timer 1 expired Active timer 2 expired Inactive timer 2 expired Ringing ...
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Si3215 SCLK CS SDI SDO SCLK CS SDI SDO High Impedance 44 Don't Care High Impedance Figure 24. Serial Write 8-Bit Mode Don't Care ...
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SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – C7 ...
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Si3215 2.11. PCM Interface The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as the PCM Mode Select (direct Register ...
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PCLK FSYNC PCLK_CNT 0 1 DRX DTX HI-Z Figure 29. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) PCLK FSYNC PCLK_CNT 0 1 DRX MSB DTX HI-Z Figure 30. GCI Example, Timeslot 1 (TXS/RXS = 0) 2.12. Companding ...
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Si3215 Table 31. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Table 32. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 Notes: ...
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Si3215 3. Control Registers Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 1 PCM Mode Select 2 PCM Transmit Start Count—Low Byte 3 PCM Transmit Start Count—High Byte 4 ...
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Table 33. Direct Register Summary (Continued) Register Name 31 Indirect Address Status 32 Oscillator 1 Control 33 Oscillator 2 Control 34 Ringing Oscillator Control 36 Oscillator 1 Active Timer—Low Byte 37 Oscillator 1 Active Timer—High Byte 38 Oscillator 1 Inactive ...
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Si3215 Table 33. Direct Register Summary (Continued) Register Name 68 Loop Closure/Ring Trip Detect Status 69 Loop Closure Debounce Interval 70 Ring Trip Detect Debounce Interval 71 Loop Current Limit 72 On-Hook Line Voltage 73 Common Mode Voltage 74 High ...
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Table 33. Direct Register Summary (Continued) Register Name 96 Calibration Control/ Status Register 1 97 Calibration Control/ Status Register 2 98 RING Gain Mismatch Cal- ibration Result 99 TIP Gain Mismatch Calibration Result 100 Differential Loop Current Gain Calibration Result ...
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Si3215 Register 0. SPI Mode Select Bit D7 D6 Name SPIDC SPIM Type R/W R/W Reset settings = 00xx_xxxx Bit Name 7 SPIDC SPI Daisy Chain Mode Enable Disable SPI daisy chain mode Enable SPI daisy ...
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Register 1. PCM Mode Select Bit D7 D6 Name PNI2 PCME Type R Reset settings = 1000_1000 Bit Name 7 PNI2 Part Number Identification Si3210 family 1 = Si3215 family 6 Reserved Read returns zero. 5 PCME ...
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Si3215 Register 3. PCM Transmit Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 TXS[9:8] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following ...
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Register 6. Part Number Identification Bit D7 D6 Name PNI[2:0] Type R Reset settings = 0xx0_0000 Bit Name 7:5 PNI[2:0] Part Number Identification. Note: PNI[2] can be read in direct Register 1. PNI[1:0] can be read in direct Register 0. ...
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Si3215 Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHDF HPF ...
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Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off ...
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Si3215 Register 11. Hybrid Control Bit D7 D6 Name HYBP[2:0] Type Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB ...
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Register 14. Powerdown Control 1 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 DCOF DC-DC Converter Power-Off Control 0 = Automatic power control Override automatic control and force dc-dc ...
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Si3215 Register 15. Powerdown Control 2 Bit D7 D6 Name ADCM Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual ...
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Register 18. Interrupt Status 1 Bit D7 D6 Name RGIP Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 RGIP Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Si3215 Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Q4AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDP Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has ...
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Si3215 Register 21. Interrupt Enable 1 Bit D7 D6 Name RGIE Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 RGIE Ringing Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 4 RGAE ...
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Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Q4AE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE Power Alarm ...
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Si3215 Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 Reserved ...
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Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into ...
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Si3215 Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect ...
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Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 REL Oscillator 1 ...
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Si3215 Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. ...
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Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS RDAC Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 Reserved ...
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Si3215 Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µs Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name ...
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Register 39. Oscillator 1 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[15:8] Oscillator 1 Inactive Timer. Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 ...
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Si3215 Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µs Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name ...
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Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit ...
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Si3215 Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register ...
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Register 64. Linefeed Control Bit D7 D6 Name LFS[2:0] Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real time linefeed state. Automatic operations may cause actual linefeed ...
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Si3215 Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. ...
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Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. This bit selects the programmable range for ...
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Si3215 Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM MNDIF Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which ...
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Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the real time output of ...
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Si3215 Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum ...
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Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity ...
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Si3215 Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be ...
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Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the ...
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Si3215 Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage ...
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Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the real time voltage at TIP with respect to ground. The range (0x00) ...
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Si3215 Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the real time voltage ...
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Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the real time current through Q3. The range (0x00) to 9.59 ...
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Si3215 Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the real time current through Q6. The range (0x00) to ...
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Register 93. DC-DC Converter Switching Delay Bit D7 D6 Name DCCAL DCPOL Type R/W Reset settings = 0001_0100 (Si3215) Reset settings = 0011_0100 (Si3215M) Bit Name 7 DCCAL DC-DC Converter Peak Current Monitor Calibration Status. Writing a one to this ...
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Si3215 Register 94. DC-DC Converter PWM Pulse Width Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width. Pulse width of DCDRV is given (DCPW – DCTOF – ...
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Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL CALSP Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 ...
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Si3215 Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1111 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled ...
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Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current. Register 99. TIP Gain Mismatch Calibration ...
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Si3215 Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result. Register 102. Current Limit Calibration Result ...
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Register 104. Analog DAC/ADC Offset Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. 0 ...
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Si3215 Register 108. Enhancement Enable Bit D7 D6 Name ILIMEN FSKEN DCSU Type R/W R/W Reset settings = 0000_0000 Bit Name 7 ILIMEN Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the end ...
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Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. ...
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Si3215 4.1. Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. ...
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Table 36. Oscillator Indirect Registers Description (Continued) Address 7 Ringing Oscillator Frequency Coefficient. Sets ringing generator frequency. 8 Ringing Oscillator Amplitude Register. Sets ringing generator signal amplitude. 9 Ringing Oscillator Initial Phase Register. Sets initial phase of ringing generator signal. ...
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Si3215 4.3. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas ...
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Table 40. SLIC Control Indirect Registers Description (Continued) Addr. 20 Power Alarm Threshold for Transistors Q3 and Q4. 21 Power Alarm Threshold for Transistors Q5 and Q6. 22 Loop Closure Filter Coefficient. 23 Ring Trip Filter Coefficient. 24 Thermal Low ...
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Si3215 Table 42. FSK Control Indirect Registers Description Addr 69 FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener- ating a space or “0”. When the ...
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Pin Descriptions: Si3215 DTX FSYNC 2 RESET 3 SDCH 4 SDCL DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC Pin # ...
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Si3215 Pin # Pin # Name QFN TSSOP 5 9 SDCL DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the con- verter Analog Supply Voltage. DDA1 Analog power supply for internal analog circuitry. ...
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Pin # Pin # Name QFN TSSOP 24 28 ITIPP Positive TIP Current Control. Analog current output driving Q1 ITIPN Negative TIP Current Control. Analog current output driving Q4 VDDD Digital Supply Voltage. Digital power supply ...
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Si3215 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O ...
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Ordering Guide Device Description Si3215-X-FM ProSLIC Si3215-X-GM ProSLIC Si3215M-X-FM ProSLIC Si3215M-X-GM ProSLIC Si3215-FT ProSLIC Si3215-GT ProSLIC Si3215M-FT ProSLIC Si3215M-GT ProSLIC Si3215-KT ProSLIC Si3215-BT ProSLIC Si3215M-KT ProSLIC Si3215M-BT ProSLIC Si3201-FS Line Interface Si3201-GS Line Interface Si3201-KS Line Interface Si3201-BS Line ...
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... Si3215 Table 43. Evaluation Kit Ordering Guide Item Si3215PPQX-EVB Si3215PPQ1-EVB Si3215DCQX-EVB Si3215DCQ1-EVB Si3215MPPQX-EVB Si3215MPPQ1-EVB Si3215MDCQX-EVB Si3215MDCQ1-EVB 112 Supported Description ProSLIC Si3215-QFN Evaluation Board, Daughter Card Si3215-QFN Evaluation Board, Daughter Card Si3215-QFN Daughter Card Only Si3215-QFN Daughter Card Only Si3215M-QFN Evaluation Board, Daughter Card ...
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Package Outline: 38-Pin QFN Figure 31 illustrates the package details for the Si321x. Table 44 lists the values for the dimensions shown in the illustration. Figure 31. 38-Pin Quad Flat No-Lead Package (QFN) Table 44. Package Diagram Dimensions Symbol ...
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Si3215 9. Package Outline: 38-Pin TSSOP Figure 32 illustrates the package details for the Si321x. Table 45 lists the values for the dimensions shown in the illustration. E/2 2x ddd aaa C Seating Plane C ...
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Package Outline: 16-Pin ESOIC Figure 33 illustrates the package details for the Si3201. Table 46 lists the values for the dimensions shown in the illustration . –A– D ...
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Si3215 OCUMENT HANGE IST Revision 0.9 to Revision 0.91 Separated the Si3216/15 document into two data sheets. Added QFN package graphic to cover page. Corrected EVB ordering part numbers. Revision 0.91 to Revision 0.92 Figure 12, “Si3215/Si3215M ...
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N : OTES Rev. 0.92 Si3215 117 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...