SI3216PPQ1-EVB Silicon Laboratories Inc, SI3216PPQ1-EVB Datasheet
SI3216PPQ1-EVB
Specifications of SI3216PPQ1-EVB
Related parts for SI3216PPQ1-EVB
SI3216PPQ1-EVB Summary of contents
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P SLIC GRA INGING Features Dual-mode wideband ( kHz)/ narrowband (200 Hz to 3.4 kHz) ...
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Si3216 2 Rev. 1.0 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si3216 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage 2 Operating Temperature Range Storage Temperature Range TSSOP-38 Thermal Resistance, Typical QFN-38 Thermal Resistance, Typical 2 ...
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Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3216 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply ...
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Si3216 Table 3. AC Characteristics—Wideband Audio Mode: Si3216 ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter TX/RX Performance—Wideband Audio Mode Overload Level ...
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Table 3. AC Characteristics—Wideband Audio Mode: Si3216 (Continued 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Noise Performance—Wideband Audio Mode 3 Idle ...
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Si3216 (dB 100 –1 –4.5 Figure 1. Transmit and Receive Path Attenuation Distortion—Wideband Mode (ms 0.25 50 100 Figure 2. Transmit and Receive Path Group Delay Distortion—Wideband Mode 8 6.4k 7k 300 4k 6.4k Rev. ...
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Table 4. AC Characteristics—Narrowband Audio Mode ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter TX/RX Performance—Narrowband Audio Mode Overload Level 1 Single ...
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Si3216 Table 4. AC Characteristics—Narrowband Audio Mode (Continued 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Noise Performance—Narrowband Audio Mode 4 Idle ...
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Figure 3. Transmit and Receive Path SNDR—Narrowband Mode Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 4. Overload Compression Performance Rev. 1.0 Acceptable Region 3 4 ...
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Si3216 Figure 5. Transmit Path Frequency Response—Narrowband Mode 12 Typical Response Typical Response Rev. 1.0 ...
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Figure 6. Receive Path Frequency Response—Narrowband Mode Rev. 1.0 Si3216 13 ...
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Si3216 Figure 7. Transmit Group Delay Distortion—Narrowband Mode Figure 8. Receive Group Delay Distortion—Narrowband Mode 14 Rev. 1.0 ...
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Table 5. Linefeed Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Loop Resistance Range R LOOP DC Loop Current Accuracy ...
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Si3216 Table 6. Monitor ADC Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity ...
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Table 9. Power Supply Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Power Supply Current Analog and Digital V ...
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Si3216 Table 10. Switching Characteristics—General Inputs 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width Note: ...
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SCLK t su1 CS SDI t d1 SDO Table 12. Switching Characteristics—PCM Highway Serial Interface V = 3. °C for K-Grade, – °C for B-Grade Parameter PCLK ...
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Si3216 PCLK FSYNC DRX DTX Figure 10. PCM Highway Interface Timing Diagram VCC 1 TIP TIP C5 22nF Protection Circuit C6 22nF 3 RING RING Notes: 1. Values and configurations for these C26 ...
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Table 13. Si3216(M) + Si3201 External Component Values Component (s) C1,C2 10 µ Ceramic Low Leakage Electrolytic, C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C15,C16,C17,C24 C18,C19 4.7 µF ...
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Si3216 Q1 Q4 5401 5401 R10 10 TIP Q6 5551 C8 R13 C5 220nF 5.1k 22nF Protection Circuit R6 C6 80.6 22nF RING Notes: 1. Values and configurations for these components can be derived from Table 18 or from “AN45: ...
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Table 14. Si3216(M) External Component Values (Continued) 200 k , 1/10 W, 1% R1,R3 100 k , 1/10 W, 1% R2,R4,R5, R102,R104,R105 80.6 , 1/4 W, 1% R6,R7 4.7 k , 1/10 W, ...
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Si3216 Table 15. Si321x BJT/Inductor DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C10* C14* C25* R16 R17 1/10 W, ±5% (See “AN45: Design Guide for The Si3210 DC- DC Converter” or Table 20 for value ...
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Table 16. Si321xM MOSFET/Transformer DC-DC Converter Component Values Component ( µF, 100 V, Electrolytic, ±20% C14* C25* 10 µF, Electrolytic, ±20% C27 470 pF, 100 V, X7R, ±20% R17 R18 1/4 W, ±5% (See DC Converter” R19,R20 1/10 ...
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Si3216 Table 17. Si321x Optional Bias Component Values Component 100 nF, 100 V, X7R, 20% C7,C8 3.0 k , 1/10 W, 5% R23,R24 The subcircuit above can be substituted into any of the ProSLIC solutions as an ...
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Functional Description The ProSLIC is a single, low-voltage CMOS device that provides all SLIC, codec, DTMF detection, and signal generation functions needed for a complete analog telephone interface. The ProSLIC performs all battery, overvoltage, ringing, supervision, codec, hybrid, and ...
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Si3216 2.1.2. Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure simplified illustration of ...
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Audio Codec A/D D/A AC Control AC Sense Control Loop TIP or RING Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown) Table 22. ProSLIC Linefeed Operations LF[2:0]* Linefeed State 000 ...
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Si3216 Table 23. Measured Real Time Linefeed Interface Characteristics Parameter Loop Voltage Sense (V – V TIP RING Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense BAT Battery Voltage Sense ...
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Table 24. Associated Power Monitoring and Power Fault Registers Parameter Power Monitor Pointer Line Power Monitor Output Power Alarm Threshold, Q1 & Q2 Power Alarm Threshold, Q3 & Q4 Power Alarm Threshold, Q5 & Q6 Thermal LPF Pole, Q1 & ...
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Si3216 LCS Input ISP_OUT Signal LVS Processor LFS LCVE 2.1.6. Loop Closure Detection A loop closure event signals that the terminal equipment has gone off-hook during On-Hook Transmission or On- Hook Active states. The ProSLIC performs loop closure detection digitally ...
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Linefeed Calibration An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL bit in direct Register 96. Upon completion of the calibration cycle, this bit is automatically reset ...
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Si3216 power supply (number of REN supported). For this solution, an n-channel power MOSFET (M1) switches the current flow through a power transformer T1 specified in “AN45: Design Guide for the Si3210/15/16 DC-DC Converter” and includes several taps ...
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Constant I Region V BATL TRACK=0 V Figure 19. V Table 27. Associated Relevant DC-DC Converter Registers Parameter DC-DC Converter Power-Off Control DC-DC Converter Calibration Enable/Status DC-DC Converter PWM Period DC-DC Converter Min. Off Time High Battery Voltage—V BATH Low ...
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Si3216 2.2.5. DC-DC Converter Enhancements The ProSLIC supports two selectable enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by ...
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Oscillator Frequency and Amplitude Each of the two-tone generators contains a two-pole resonant oscillator circuit with frequency and amplitude. These two-tone generators are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the ...
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Si3216 Table 28. Associated Tone Generator Registers Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude ...
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Enhanced FSK Waveform Generation Enhanced FSK generation capabilities can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REN = 1 (direct Register 32, bit 6). In this mode, the user can define mark (1) ...
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Si3216 Table 29. Registers for Ringing Generation Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery ...
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V TIP-RING V ROFF T=1/freq t RISE Figure 22. Trapezoidal Ringing Waveform To configure the ProSLIC for trapezoidal ringing, the user should follow the same basic procedure as in the Sinusoidal Ringing section, but using the following equations: 1 ...
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Si3216 BATH AC,PK ROFF The ProSLIC is designed to create a fully-balanced ringing waveform, meaning that the TIP and RING common mode voltage TIP RING voltage is referred ...
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Table 30. Associated Registers for Ring Trip Detection Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Detect Debounce Interval Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Note: The ProSLIC uses registers ...
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Si3216 44 Rev. 1.0 ...
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Receive Path In the receive path, digital voice is expanded from µ/A- law if enabled. DACG is the receive path programmable gain amplifier which can be programmed from – dB. A 16-bit signal is then ...
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Si3216 subscriber loop via the ITIPP and IRINGP pins through an off-chip current buffer (I ), which is implemented BUF using transistors Q1 and Q2 (see Figure on page 22 referenced to an off-chip resistor (R m The ...
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The second byte of the pair is the data byte. During a read operation, the SDO becomes active, and the 8-bit contents of the register are driven out ...
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Si3216 SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – ...
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PCM Interface The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as the PCM Mode Select (direct Register 1), ...
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Si3216 Table 32. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Table 33. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 Notes: ...
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Si3216 3. Control Registers Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 1 PCM Mode Select 2 PCM Transmit Start Count—Low Byte 3 PCM Transmit Start Count—High Byte 4 ...
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Table 34. Direct Register Summary (Continued) Register Name 31 Indirect Address Status 32 Oscillator 1 Control 33 Oscillator 2 Control 34 Ringing Oscillator Control 36 Oscillator 1 Active Timer—Low Byte 37 Oscillator 1 Active Timer—High Byte 38 Oscillator 1 Inactive ...
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Si3216 Table 34. Direct Register Summary (Continued) Register Name 68 Loop Closure/Ring Trip Detect Status 69 Loop Closure Debounce Interval 70 Ring Trip Detect Debounce Interval 71 Loop Current Limit 72 On-Hook Line Voltage 73 Common Mode Voltage 74 High ...
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Table 34. Direct Register Summary (Continued) Register Name 96 Calibration Control/ Status Register 1 97 Calibration Control/ Status Register 2 98 RING Gain Mismatch Calibration Result 99 TIP Gain Mismatch Calibration Result 100 Differential Loop Current Gain Calibration Result 101 ...
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Si3216 Register 0. SPI Mode Select Bit D7 D6 Name SPIDC SPIM Type R/W R/W Reset settings = 00xx_xxxx Bit Name 7 SPIDC SPI Daisy Chain Mode Enable Disable SPI daisy chain mode Enable SPI daisy ...
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Register 1. PCM Mode Select Bit D7 D6 Name PNI2 WBE PCME Type R R/W R/W Reset settings = 1000_1000 Bit Name 7 PNI2 Part Number Identification 2. Note: PNI[2:0] can be read in direct Register Si3210, ...
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Si3216 Register 2. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data trans- mission ...
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Register 5. PCM Receive Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[9:8] PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC ...
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Si3216 Register 8. Audio Path Loopback Control Bit D7 D6 Name Type Reset settings = 0000_0010 Bit Name 7:3 Reserved Read returns zero. 2 ALM2 Analog Loopback Mode 2. (See Figure 24 on page 44 Full analog loopback ...
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Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP TXM Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHDF ...
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Si3216 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off ...
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Register 11. Hybrid Control Bit D7 D6 Name HYBP[2:0] Type R/W Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB ...
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Si3216 Register 14. Powerdown Control 1 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 DCOF DC-DC Converter Power-Off Control Automatic power control Override automatic control and force ...
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Register 15. Powerdown Control 2 Bit D7 D6 Name ADCM Type R/W Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual ...
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Si3216 Register 18. Interrupt Status 1 Bit D7 D6 Name RGIP Type R/W Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 RGIP Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. ...
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Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Q4AP Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Si3216 Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDP Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request ...
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Register 21. Interrupt Enable 1 Bit D7 D6 Name RGIE Type R/W Reset settings = 0000_0000 Bit Name 7:6 Reserved Read/write bit with no function. 5 RGIE Ringing Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. ...
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Si3216 Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Q4AE Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE ...
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Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 Reserved Read/write ...
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Si3216 Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA ...
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Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register ...
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Si3216 Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL OZ1 Type R R/W R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 ...
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Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 OZ2 Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns ...
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Si3216 Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS RDAC Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 ...
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Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µs Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type ...
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Si3216 Register 39. Oscillator 1 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[15:8] Oscillator 1 Inactive Timer. Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = ...
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Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µs Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type ...
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Si3216 Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 ...
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Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, ...
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Si3216 Register 64. Linefeed Control Bit D7 D6 Name LFS[2:0] Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real time linefeed state. Automatic operations may cause actual ...
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Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH CBY Type R/W R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins ...
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Si3216 Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. (See Figure 19 on page 35.) This bit selects the programmable range ...
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Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM MNDIF Type R/W R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which ...
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Si3216 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. The state of this bit reflects the real time ...
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Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady ...
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Si3216 Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage ...
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Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. V equal to V ...
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Si3216 Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of ...
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Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (V ...
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Si3216 Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the real time voltage at TIP with respect to ground. The range ...
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Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the real time voltage ground. ...
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Si3216 Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the real time current through Q3. The range (0x00) to ...
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Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the real time current through Q6. The range (0x00) to 80.58 ...
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Si3216 Register 93. DC-DC Converter Switching Delay Bit D7 D6 Name DCCAL DCPOL Type R/W Reset settings = 0001_0100 (Si3216) Reset settings = 0011_0100 (Si3216M) Bit Name 7 DCCAL DC-DC Converter Peak Current Monitor Calibration Status. Writing a one to ...
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Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL CALSP Type R/W R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. ...
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Si3216 Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1110 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled ...
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Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current. Register 99. TIP Gain Mismatch Calibration ...
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Si3216 Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result. Register 102. Current Limit Calibration Result ...
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Register 104. Analog DAC/ADC Offset Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. 0 ...
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Si3216 Register 108. Enhancement Enable Bit D7 D6 Name ILIMEN FSKEN DCSU Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 ILIMEN Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the ...
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Bit Name 1 DCFIL DC-DC Converter Squelch. When enabled, this bit squelches noise in the audio band from the dc-dc converter con- trol loop Voice band squelch disabled Voice band squelch enabled. 0 HYSTEN Loop Closure ...
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Si3216 4. Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect ...
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Table 36. Oscillator Indirect Registers Summary (Continued) Addr. D15 D14 D13 D12 D11 Table 37. Oscillator Indirect Registers Description Addr. 0 Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. 1 Oscillator 1 Amplitude Register. Sets tone ...
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Si3216 Table 39. Digital Programmable Gain/Attenuation Indirect Registers Description Addr. 13 Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive path. The digitized signal is effectively mul- tiplied by DACG to achieve gain/attenuation. A value ...
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SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote ...
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Si3216 Table 41. SLIC Control Indirect Registers Description (Continued) Addr. 19 Power Alarm Threshold for Transistors Q1 and Q2. 20 Power Alarm Threshold for Transistors Q3 and Q4. 21 Power Alarm Threshold for Transistors Q5 and Q6. 22 Loop Closure ...
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FSK Control For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL ...
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Si3216 5. Pin Descriptions: Si3216 QFN DTX FSYNC 2 RESET 3 SDCH 4 SDCL DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC ...
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Pin # Pin # Name QFN TSSOP 5 9 SDCL DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the con- verter VDDA1 Analog Supply Voltage. Analog power supply for internal analog circuitry ...
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Si3216 Pin # Pin # Name QFN TSSOP 24 28 ITIPP Positive TIP Current Control. Analog current output driving Q1 ITIPN Negative TIP Current Control. Analog current output driving Q4 VDDD Digital Supply Voltage. Digital power ...
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Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I RING I/O 4 VBAT 5 VBATH 7 GND 8 VDD 10 SRINGE O 11 STIPE O 13 IRINGN I 14 IRINGP I ...
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Si3216 7. Ordering Guides Device Description Wideband Codec Si3216-C-FM ProSLIC Si3216-C-GM ProSLIC Si3216M-C-FM ProSLIC Si3216M-C-GM ProSLIC Si3216-KT ProSLIC Si3216-BT ProSLIC Si3216-FT ProSLIC Si3216-GT ProSLIC Si3216M-KT ProSLIC Si3216M-BT ProSLIC Si3216M-FT ProSLIC Si3216M-GT ProSLIC Si3201-KS Linefeed Interface Si3201-BS Linefeed Interface Si3201-FS Linefeed ...
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... Table 45. Evaluation Kit Ordering Guide Item Supported ProSLIC Si3216PPQX-EVB Si3216-QFN Si3216PPQ1-EVB Si3216-QFN Si3216DCQX-EVB Si3216-QFN Si3216DCQ1-EVB Si3216-QFN Si3216MPPQX-EVB Si3216M-QFN Si3216MPPQ1-EVB Si3216M-QFN Si3216MDCQ1-EVB Si3216M-QFN Si3216MDCQX-EVB Si3216M-QFN Si3216PPTX-EVB Si3216-TSSOP Si3216PPT1-EVB Si3216-TSSOP Si3216DCX-EVB Si3216-TSSOP Si3216DC1-EVB Si3216-TSSOP Description Eval Board, Daughter Card Eval Board, Daughter Card ...
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Si3216 8. Package Outline: 38-Pin QFN Figure 30 illustrates the package details for the Si321x. Table 46 lists the values for the dimensions shown in the illustration. Figure 30. 38-Pin Quad Flat No-Lead Package (QFN) Table 46. Package Diagram Dimensions ...
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Package Outline: 38-Pin TSSOP Figure 31 illustrates the package details for the Si321x. Table 47 lists the values for the dimensions shown in the illustration. E/2 2x ddd aaa C Seating Plane C Figure ...
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Si3216 10. Package Outline: 16-Pin ESOIC Figure 32 illustrates the package details for the Si3201. Table 48 lists the values for the dimensions shown in the illustration . –A– ...
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Silicon Labs Si3216 Support Documentation AN32: Si321x Frequency Shift Keying (FSK) Modulation AN33: Si321x Neon Flashing AN34: Si321x Hardware Reference Guide AN35: Si321x User’s Quick Reference Guide AN39: Connecting the ProSLIC to the W ...
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Si3216 OCUMENT HANGE IST Revision 0.61 to Revision 0.9 Separated the Si3216/15 document into two data sheets. Added Quad Flat No-Lead (QFN) package. Removed references to Si3215. Updated Figure 11 on page 20. ...
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N : OTES Rev. 1.0 Si3216 121 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are registered trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...