DS64EV400-EVK National Semiconductor, DS64EV400-EVK Datasheet
DS64EV400-EVK
Specifications of DS64EV400-EVK
Related parts for DS64EV400-EVK
DS64EV400-EVK Summary of contents
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... PRBS-31, and bal- anced codes such as 8b/10b. The device uses differential current-mode logic (CML) inputs and outputs. The DS64EV400 is available 48-pin leadless LLP package. Power is supplied from either a 2.5V or 3.3V supply. Simplified Application Diagram © ...
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Pin Descriptions Pin Name Pin # I/O, Type HIGH SPEED DIFFERENTIAL I/O IN_0 CML IN_0– 2 IN_1 CML IN_1– 5 IN_2 CML IN_2– 9 IN_3 CML IN_3– 12 OUT_0 CML ...
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... NSID Package Type, Qty Size DS64EV400SQ 48–pin LLP ( 0.8 mm, 0.5 mm pitch, reel of 250 DS64EV400SQX 48–pin LLP ( 0.8 mm, 0.5 mm pitch, reel of 2500 Data input/output (bi-directional). Internally pulled high. Clock input. Internally pulled high. Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When pulled low, access to the equalizer SMBus registers are disabled. Please refer to “ ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS Input Voltage CMOS Output Voltage CML Input/Output Voltage Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 Seconds) Electrical Characteristics Over recommended operating supply and temperature ranges with default register settings unless other specified ...
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Symbol Parameter CML RECEIVER INPUTS (IN_n+, IN_n-) V Source Transmit Launch Signal TX Level (IN diff) V Input Threshold Voltage INTRE V Supply Voltage of Transmitter to DDTX EQ V Input Common Mode Voltage ICMDC R Differential Input Return Loss ...
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Symbol Parameter SIGNAL DETECT and ENABLE TIMING t Input OFF to ON detect — SD ZISD Output High Response Time t Input ON to OFF detect — SD IZSD Output Low Response Time t EN High to Output ON Response ...
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Electrical Characteristics — Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter SERIAL BUS INTERFACE DC SPECIFICATIONS V Data, Clock Input Low Voltage IL V Data, Clock Input High Voltage IH I Current ...
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... When communication to other devices on the SMBus is active, the CS signal for the DS32EV400s must be driven Low. The address byte for all DS64EV400s is AC'h. Based on the SMBus 2.0 specification, the DS64EV400 has a 7-bit slave address of 1010110'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 1100'b or AC'h ...
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Name Address Default Type Bit 7 0x00 0x00 RO Status 0x01 0x00 RO Status Status 0x02 0x00 RO Enable/ 0x03 0x44 RW Boost ( Enable/ 0x04 0x44 RW Boost ( 0x05 0x00 RW Signal Detect 0x06 ...
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FIGURE 1. Test Setup Diagram FIGURE 2. CML Output Transition Times FIGURE 3. Propagation Delay Timing Diagram FIGURE 4. Signal Detect (SD) Delay Timing Diagram 10 30032027 30032002 30032003 30032004 ...
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FIGURE 5. Enable (EN) Delay Timing Diagram FIGURE 6. Simplified Receiver Input Termination Circuit FIGURE 7. SMBus Timing Parameters 11 30032005 300320017 www.national.com 300320018 ...
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... FEB is internally pulled High (default setting); therefore if left unconnected, the boost settings are controlled by the Boost Set pins (BST_[0:2]). The eight levels of boost settings enables the DS64EV400 to address a wide range of media loss and data rates. TABLE 2. EQ Boost Control Table ...
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... ENn pin, this will enable the equalizer, limiting amplifier, and output buffer on the data channels; thus the 90 DS64EV400 will automatically enter the ACTIVE state. If the 75 input signal swing falls below the SD_OFF threshold level, then the SDn output will be asserted Low, causing the channel to be placed in the STANDBY state ...
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... These capac- itors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as possible to the DS64EV400. DC COUPLING The DS64EV400 supports both AC coupling with external ac coupling capacitor, and DC coupling to its upstream driver, or downstream receiver ...
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Typical Performance Eye Diagrams and Curves Figure 8. Equalized Signal (40 In FR4, 2.5Gbps, PRBS7, 0x07 Setting) Figure 10. Equalized Signal (40 In FR4, 6.4 Gbps, PRBS7, 0x06 Setting) Figure 12. Equalized Signal (30 In FR4, 10 Gbps, PRBS7, 0x06 ...
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Figure 14. Equalized Signal (32 In Tyco XAUI Backplane, 6.25 Gbps, PRBS7, 0x06 Setting) Figure 15. DJ vs. EQ Setting (10 Gbps) www.national.com 30032014 30032015 Figure 16 Setting (6.4 Gbps) 16 30032016 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 48-pin LLP Package ( 0.8 mm, 0.5 mm pitch) Order Number DS64EV400SQ Package Number SQA48D 17 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...