DS50EV401-EVK National Semiconductor, DS50EV401-EVK Datasheet

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DS50EV401-EVK

Manufacturer Part Number
DS50EV401-EVK
Description
KIT EVAL DS50EV401 EQUALIZER
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheet

Specifications of DS50EV401-EVK

Main Purpose
Interface, Cable Equalizer
Utilized Ic / Part
DS50EV401
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
© 2010 National Semiconductor Corporation
2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane
Equalizer
General Description
The DS50EV401 is a low power, programmable equalizer
specifically designed to reduce inter-symbol interference (ISI)
induced by a variety of interconnect media. In all modes, the
equalizer can operate, error free, with an input eye that is
completely closed by interconnect ISI. The MODE control, al-
lows the user to select between equalization settings for 8.0
Gbps operation or 2.5 Gbps / 5.0 Gbps operation.
The DS50EV401 uses Current-mode logic (CML) on both in-
put and output ports, which provide constant 50 ohm single-
ended impedance to AC ground. Differential signaling is
implemented through out the entire signal path to minimize
supply induced jitter. The DS50EV401 is available in a 7mm
x 7mm 48-pin leadless LLP package, and is powered from a
single power supply of either 3.3 or 2.5V.
Application Diagram
300505
DS50EV401
Features
Automatic power management on an individual lane basis
Data rate optimized equalization
Operates over 7 meter of 24 AWG Twin-ax Cables up to
8 Gbps
Typical residual deterministic jitter:
8 kV HBM ESD protection
-40 to 85°C operating temperature range
7 mm x 7 mm 48-pin leadless LLP package
Single power supply of either 3.3V or 2.5V
Low power (typically 95 mW per channel at 2.5V V
0.18 UI @ 8 Gbps w/ 30” of FR4
0.18 UI @ 5 Gbps w/ 40” of FR4
0.16 UI @ 2.5 Gbps w/ 40” of FR4
30050550
www.national.com
June 8, 2010
DD
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Related parts for DS50EV401-EVK

DS50EV401-EVK Summary of contents

Page 1

... AC ground. Differential signaling is implemented through out the entire signal path to minimize supply induced jitter. The DS50EV401 is available in a 7mm x 7mm 48-pin leadless LLP package, and is powered from a single power supply of either 3.3 or 2.5V. ...

Page 2

Pin Descriptions Pin Name Pin Number I/O, Type HIGH SPEED DIFFERENTIAL I/O IN_0 CML IN_0- 2 IN_1 CML IN_1- 5 IN_2 CML IN_2- 9 IN_3 CML IN_3- 12 OUT_0 CML ...

Page 3

... Note Input O = Output Connection Diagram Ordering Information NSID Package DS50EV401SQ 48 Lead LLP Package DS50EV401SQE 48 Lead LLP Package DS50EV401SQX 48 Lead LLP Package Description V = 2.5V ± 3.3V ± 10%. V pins should be tied path. A 0.1μF bypass capacitor should be connected between each V Ground reference. GND should be tied to a solid ground plane through a low impedance path ...

Page 4

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS Input Voltage LVCMOS Output Voltage CML Input/Output Voltage Junction Temperature Storage Temperature ESD Rating Electrical Characteristics Over recommended operating supply and temperature ranges with default register settings unless other specified. ...

Page 5

Symbol Parameter CML OUTPUTS (OUT_n+, OUT_n-) V Output Voltage Swing O V Output Common-Mode Voltage OCM Transition Time Output Resistance O R Differential Output Return Loss LO t Differential Low to High PLHD Propagation ...

Page 6

Timing Diagrams www.national.com FIGURE 1. Test Setup Diagram FIGURE 2. CML Output Transition Times FIGURE 3. Propagation Delay Timing Diagram 6 30050527 30050502 30050503 ...

Page 7

FIGURE 4. Idle Timing Diagram FIGURE 5. CML Output Swings at A/B 7 30050504 30050560 www.national.com ...

Page 8

... The equal- izer is designed to open an input eye that is completely closed due to inter-symbol interference (ISI) induced by the channel Data Channels The DS50EV401 consists of four data channels. Each chan- nel provides input termination, receiver equalization, signal limiting, offset cancellation, and a CML output driver, as shown in Figure 6 ...

Page 9

... Additionally, three capacitors with capac- itance in the range of 2.2 μ μF should be incorporated in the power supply bypassing design as well. These capac- itors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as possible to the DS50EV401. 9 and GND planes create pin such that the ca- DD www ...

Page 10

The CML inputs are AC coupled to the device as shown in Figure 7. Internal to the device are 50Ω terminations to V The CML outputs drive 100 Ω transmission lines and are AC coupled and terminated at their load. ...

Page 11

FR4 / BACKPLANE Typical Performance Eye Diagrams The plots show the unequalized and equalized eye patterns for various interconnects as noted. Unequalized is shown in Figure 8. Unequalized Signal (40 in FR4, 2.5 Gbps, PRBS7) Figure 10. Unequalized Signal (40 ...

Page 12

Twin-AX CABLES Typical Performance Eye Diagrams The plots show the unequalized and equalized eye patterns for various interconnects as noted. Unequalized is shown in Figure 14. Unequalized Signal ( AWG Twin-AX Cable, 2.5 Gbps, PRBS7) Figure 16. Unequalized ...

Page 13

... Physical Dimensions inches (millimeters) unless otherwise noted 7mm x 7mm 48-pin LLP Package Order Number DS50EV401SQ Package Number SQA48D 13 www.national.com ...

Page 14

... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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