AD9246-125EBZ Analog Devices Inc, AD9246-125EBZ Datasheet
AD9246-125EBZ
Specifications of AD9246-125EBZ
Related parts for AD9246-125EBZ
AD9246-125EBZ Summary of contents
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... Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes GENERAL DESCRIPTION The AD9246 is a monolithic, single 1.8 V supply, 14-bit, 80 MSPS/ 105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on-chip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range ...
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... AD9246 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Diagram ........................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Equivalent Circuits ......................................................................... 10 Typical Performance Characteristics ........................................... 11 Theory of Operation ...
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... Deleted Figures 37, 38, 40, 41 ........................................................14 Deleted Figure 46 ............................................................................15 Deleted Figure 52 ............................................................................16 Changes to Figure 41 ......................................................................17 Changes to Figure 46 ......................................................................19 Inserted Figure 54 ...........................................................................21 Added Data Clock Output (DCO) Section .................................22 Changes to Table 15 ........................................................................25 Changes to Table 16 ........................................................................39 Changes to the Ordering Guide ....................................................42 4/06—Revision 0: Initial Version Rev Page AD9246 ...
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... Rev Page AD9246BCPZ-125 Max Min Typ Max Unit 14 Bits Guaranteed ±0.8 ±0.3 ±0.8 % FSR ±5.0 ±0.6 ±4.2 % FSR ±1.0 ±1.0 LSB ±0.4 LSB ±5.0 ± ...
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... Full 85 − 25°C −90 25°C −90 25°C 87 25°C 83 25°C 650 Rev Page AD9246 AD9246BCPZ-125 Typ Max Min Typ Max 71.9 71.9 71.9 71.7 69.5 71.6 71.6 70.9 70.8 71.1 71.1 70.8 70.6 68.5 70.6 70 ...
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... Full Full Full Full Full Full Full Full = 50 μA) Full = 0.5 mA) Full Full Full = 50 μA) Full = 0.5 mA) Full Full Full Rev Page AD9246BCPZ-80/105/125 Min Typ Max CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − 0.3 AVDD + 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 8 ...
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... – – – – CLK AD9246 Unit Max 125 MSPS 125 MSPS ns 5.6 ns 4 cycles ns ps rms μs Cycles ...
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... AD9246 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating ELECTRICAL AVDD to AGND −0 +2.0 V DRVDD to DGND −0 +3.9 V AGND to DGND −0 +0.3 V AVDD to DRVDD −3 +2 through D13 to DGND −0 DRVDD + 0.3 V DCO to DGND −0 DRVDD + 0 DGND −0 DRVDD + 0.3 V CLK+ to AGND −0 +3.9 V CLK− ...
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... Common-Mode Level Bias Output. External Bias Resistor Connection kΩ resistor must be connected between this pin and analog ground (AGND). Power-Down Function Select. Clock Input (+). Clock Input (−). Output Enable (Active Low). Data Clock Output. Rev Page AD9246 36 PDWN 35 RBIAS 34 CML 33 AVDD ...
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... AD9246 EQUIVALENT CIRCUITS VIN Figure 4. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 5. Equivalent Clock Input Circuit DRVDD 1kΩ SDIO/DCS Figure 6. Equivalent SDIO/DCS Input Circuit DRVDD DRGND Figure 7. Equivalent Digital Output Circuit SCLK/DFS OEB PDWN Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit CSB CLK– ...
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... MHz Figure 15. AD9246-125 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 46.875 62.500 = 30.3 MHz Figure 16. AD9246-125 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 46.875 62.500 = 70.3 MHz Figure 17. AD9246-125 Single-Tone FFT with f IN Rev ...
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... Figure 20. AD9246 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with f = 2.4 MHz IN 46.875 62.500 = 225.3 MHz Figure 21. AD9246 Single-Tone SNR/SFDR vs. Input Frequency (f IN 46.875 62.500 = 300.3 MHz Figure 22. AD9246 Single-Tone SNR/SFDR vs. Input Frequency ( –30 –20 –10 Rev Page SFDR = +25°C 90 SFDR = –40°C 85 SFDR = +85° ...
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... MSPS IN S 46.875 62.500 = 29.1 MHz 32.1 MHz Figure 27. AD9246 Two-Tone SFDR/IMD vs. Input Amplitude (AIN) IN2 46.875 62.500 = 172.1 MHz Figure 28. AD9246 Two-Tone SFDR/IMD vs. Input Amplitude (AIN) IN2 –100 –120 46.08 61.44 Rev Page SFDR (dBc) –20 –40 IMD3 (dBc) – ...
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... MHz IN 100 SFDR DCS SFDR DCS OFF SNR DCS OFF DUTY CYCLE (%) Figure 31. AD9246 SNR/SFDR vs. Duty Cycle with f 90 SFDR SNR 70 0.5 0.6 0.7 0.8 0.9 1.0 INPUT COMMON-MODE VOLTAGE (V) Figure 32. AD9246 SNR/SFDR vs. Input Common Mode (VCM) with MHz ...
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... It is recommended that REFT be decoupled to REFB by a 0.1 μF capacitor, as described in the Layout Considerations section. Input Common Mode The analog inputs of the AD9246 are not internally dc-biased. In ac-coupled applications, the user must provide this bias externally. Setting the device such that V recommended for optimum performance ...
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... ADC. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9246 (see Figure 37), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...
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... A stable and accurate voltage reference is built into the AD9246. The input range is adjustable by varying the reference voltage applied to the AD9246, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the following sections ...
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... V p-p differential. This helps prevent the large voltage 1.5 2.0 swings of the clock from feeding through to other portions of the AD9246, while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance. Rev Page VREF = 1V ...
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... Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9246 contains a duty cycle stabilizer (DCS) that retimes the nonsampling, or falling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9246 ...
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... Figure 51. SNR vs. Input Frequency and Jitter Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9246. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. ...
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... Digital Output Enable Function (OEB) The AD9246 has three-state ability. If the OEB pin is low, the output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. This is not intended for rapid access to the data bus. Note that OEB is referenced to the digital supplies (DRVDD) and should not exceed that supply voltage ...
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... AD9246 TIMING The lowest typical conversion rate of the AD9246 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. The AD9246 provides latched data outputs with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (t ) after the rising edge of the clock signal. ...
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... The pins described in Table 13 comprise the physical interface between the user’s programming device and the serial port of the AD9246. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. ...
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... AD9246 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight address locations. The memory map is roughly divided into three sections: the chip configuration registers map (Address 0x00 to Address 0x02), the device index and transfer registers map (Address 0xFF), and the ADC functions map (Address 0x08 to Address 0x18) ...
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... Open Open Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 0 = Off 0 = Off (Default) (Default 8-bit Chip ID Bits 7:0 (AD9246 = 0x00), (default) Open Open Child ID Open 0 = 125 MSPS 105 MSPS Open Open Open Open PDWN Open Open Internal power-down mode 000—normal (power-up, Default) 0— ...
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... AD9246 Addr. Bit 7 (Hex) Parameter Name (MSB) Flexible ADC Functions 10 offset 0D test_io 14 output_mode Output Driver Configuration 00 for DRVDD = 2 3.3 V (Default) 10 for DRVDD = 1 output_phase Output Clock Polarity 1 = inverted 0 = normal (Default) 18 VREF Internal Reference Resistor Divider 00—VREF = 1.25 V 01—VREF = 1.5 V 10—VREF = 1.75 V 11— ...
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... The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 38. RBIAS The AD9246 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...
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... AD9246 EVALUATION BOARD The AD9246 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a double balun configuration (default) or through the AD8352 differential driver. The ADC can also be driven in a single-ended fashion ...
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... DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9246 Rev. A evaluation board. POWER Connect the switching power supply that is supplied in the evaluation kit between a rated 100 240 V ac wall outlet and P500. ...
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... AD9246 1. Remove C1 and C2 in the default analog input path. 2. Populate R3 and R4 with 200 Ω resistors in the analog input path. 3. Populate the optional amplifier input path with all components except R594, R595, and C502. Note that to terminate the input path, only one of the following components should be populated: R9, R592, or the combination of R590 and R591 ...
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... SCHEMATICS RC0402 RC0402 RC040 2 RC040 2 RC0402 CC0402 2 HSMS281 2 HSMS281 RC0402 CC0402 CC0402 RC060 3 RC060 3 Figure 60. Evaluation Board Schematic, DUT Analog Inputs Rev Page AD9246 05491-072 CC0402 RC060 3 RC060 3 ...
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... AD9246 Figure 61. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface RC060 3 Rev Page 05491-073 ...
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... CC0402 CC0402 RC0402 RC060 3 CC0402 CC0402 RC060 3 RC060 3 Figure 62. Evaluation Board Schematic, DUT Clock Input CC0402 CC0402 CC0402 RC0402 RC0402 RC0402 RC0402 S0 S10 GND_PAD S10 7 VREF 32 6 RSET RC0402 RC0402 RC0402 RC0402 RC0402 RC0402 Rev Page AD9246 05491-071 CC0402 ...
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... AD9246 RC0603 SDO_CHA RC0603 CSB1_CHA RC0603 SDI_CHA RC0603 SCLK_CHA RC0603 RC0603 RC0603 RC0603 RC0603 1 2 PICVCC PICVCC 3 4 GP1 GP1 5 6 GP0 GP0 7 8 MCLR-GP3 MCLR-GP3 RC060 Figure 63. Evaluation Board Schematic, SPI Circuitry Rev Page 05491-070 RC0603 ...
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... GND GND 1 1 GND GND GND CR500 1 2 Figure 64. Evaluation Board Schematic, Power Supply Inputs Rev Page AD9246 05491-069 TP509 TP512 TP511 TP510 ...
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... AD9246 EVALUATION BOARD LAYOUTS Figure 65. Evaluation Board Layout, Primary Side Figure 66. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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... Figure 67. Evaluation Board Layout, Ground Plane Figure 68. Evaluation Board Layout, Power Plane Rev Page AD9246 ...
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... AD9246 Figure 70. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image) Figure 69. Evaluation Board Layout, Silkscreen Primary Side Rev Page ...
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... Oscillator SMT 125 MHz or 105 MHz Connector PJ-102A DC power jack Connector 10 pin Male, straight Rev Page AD9246 Supplier/Part Number ADI Panasonic LNJ314G8TRA HSMS2812 Micro Commercial Group SK33-TPMSCT-ND Micro Commercial Group S2A-TPMSTR-ND Amber LED Tyco, Raychem NANOSMDC110F-2 Murata ...
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... AD9246 Omit Item Qty. (DNP) Reference Designator 29 6 R1, R6, R563, R565, R574, R577 30 5 R2, R5, R561, R562, R571 6 R10, R11, R12, R535, R536, R575 R7, R8, R9, R502, R510, R511 33 6 R500, R501, R576, R578, R579, R581 34 4 R503, R548, R549, R550 ...
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... IC SC70 Dual buffer IC SC70 Dual buffer IC 48-pin Buffer/line TSSOP driver DUT 48-pin ADC (AD9246) LFCSP_VQ IC 16-pin Differential LFCSP_VQ amplifier Rev Page AD9246 Supplier/Part Number ADI ADP3339AKCZ-2.5 ADI ADP3339AKCZ-3.3 Microchip PIC12F629 Fairchild NC7WZ16 Fairchild NC7WZ07 Fairchild 74VCX162244 ADI AD9246BCPZ ADI AD8352ACPZ ...
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... AD9246BCPZRL7-105 –40°C to +85°C 2 AD9246BCPZ-80 –40°C to +85°C 2 AD9246BCPZRL7-80 –40°C to +85°C AD9246-125EB AD9246-105EB AD9246-80EB required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance Pb-free part. 7.00 BSC SQ 0 ...
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... NOTES Rev Page AD9246 ...
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... AD9246 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05491-0-8/06(A) Rev Page ...