AD6644ST/PCBZ Analog Devices Inc, AD6644ST/PCBZ Datasheet - Page 5

• Manufacturer Part Number: AD6644ST/PCBZ
• Description: BOARD EVAL ADC 14BIT CMOS AD6644
• Manufacturer: Analog Devices Inc

Specifications of AD6644ST/PCBZ

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 65M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2.2 Vpp
• Power (typ) @ Conditions: 1.3W @ 65MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -25°C ~ 85°C
• Utilized Ic / Part: AD6644
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
DATA READY (DRY
APERTURE DELAY
APERTURE UNCERTAINTY (JITTER)
1
2
3
4
5
6
7
AC SPECIFICATIONS
All ac specifications tested by driving ENCODE and ENCODE differentially.
AV
Table 5.
Parameter
SNR
SINAD
WORST HARMONIC (2ND or 3RD)
WORST HARMONIC (4TH or Higher)
TWO-TONE SFDR
TWO-TONE IMD REJECTION
ANALOG INPUT BANDWIDTH
1
2
3
4
See the Explanation of Test Levels section.
Several timing parameters are a function of t
To compensate for a change in duty cycle for t
ENCODE to data delay (hold time) is the absolute minimum propagation delay through the ADC.
ENCODE to data delay (setup time) is calculated relative to 65 MSPS (50% duty cycle). To calculate t
DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock correspondingly changes the duty cycle of DRY.
Data ready to data delay (t
given encode, use the following equations:
See the Explanation of Test Levels section.
AV
Analog input signal power swept from −7 dBFS to −100 dBFS.
F1 = 15 MHz, F2 = 15.5 MHz.
Data Ready to DATA Delay (Hold Time)
Data Ready to DATA Delay (Setup Time)
Newt
Analog Input
@ −1 dBFS
Analog Input
@ −1 dBFS
Analog Input
@ −1 dBFS
Analog Input
@ −1 dBFS
F1, F2 @ −7 dBFS
Newt
Newt
Newt
Newt
CC
CC
Encode = 65 MSPS (50% Duty Cycle)
Encode = 40 MSPS (50% Duty Cycle)
@ 65 MSPS (50% Duty Cycle)
@ 40 MSPS (50% Duty Cycle)
= 5 V to 5.25 V for rated ac performance.
= 5 V, DV
2
S_DR
H_DR
S_E
H_DR
S_DR
= t
= (t
= t
= (t
= t
ENC(NEW)
ENC(NEW)
ENC(NEW)
S_DR
H_DR
CC
− % Change(t
2, 3, 4
− % Change(t
− t
/2 − t
/2 − t
6
= 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; T
)/DATA, OVR
ENC
+ t
ENCH
ENCH
H_DR
S_E
+ t
+ t
(that is, for 40 MSPS, Newt
2, 4
and t
ENCH
S_DR
ENCH
H_DR
)) × t
)) × t
(that is, for 40 MSPS, Newt
(that is, for 40 MSPS, Newt
S_DR
2
ENC
) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on t
2
ENC
/2
/2
ENC
3
H_DR
3
and t
and t
15.5 MHz
15.5 MHz
Conditions
2.2 MHz
30.5 MHz
2.2 MHz
30.5 MHz
2.2 MHz
15.5 MHz
30.5 MHz
2.2 MHz
15.5 MHz
30.5 MHz
ENCH
S_DR
S_E(TYP)
.
use the following equations:
S_DR(TYP)
= 25 × 10
H_DR(TYP)
Name
t
t
t
t
H_DR
S_DR
A
J
= 12.5 × 10
= 12.5 × 10
25°C
25°C
25°C
25°C
25°C
25°C
Full
Temp
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
−9
− 15.38 × 10
Rev. D | Page 5 of 24
Temp
Full
Full
Full
Full
25°C
25°C
−9
−9
− 7.69 × 10
− 7.69 × 10
Test Level
V
II
II
V
II
V
V
II
V
V
II
V
V
V
V
−9
+ 9.8 × 10
Test Level
IV
IV
IV
IV
V
V
−9
−9
+ 5.5 × 10
+ 8.6 × 10
1
−9
S_E
= 19.4 × 10
Min
for a given encode, use the following equation:
MIN
1
−9
−9
AD6644AST-40
= 10.3 × 10
= 13.4 × 10
= −25°C, T
−9
Typ
74.5
74.0
73.5
74.5
74.0
73.0
92
90
85
93
92
92
100
90
250
Min
8.0
12.8
3.2
8.0
).
ENC
and duty cycle. To calculate t
−9
−9
).
).
MAX
Max
AD6644AST-40/65
= +85°C, unless otherwise noted.
See note
See note
13.4
10.3
Typ
100
8.6
5.5
0.2
Min
72
72
72
83
85
AD6644AST-65
7
7
Typ
74.5
74.0
73.5
74.5
74.0
73.0
92
90
85
93
92
92
100
90
250
H_DR
Max
9.4
14.2
6.5
11.3
and t
Max
AD6644
S_DR
Unit
ns
ns
ns
ns
ps
ps rms
for a
Unit
dB
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBc
MHz