CDB44800

Manufacturer Part NumberCDB44800
DescriptionBOARD EVAL FOR CS44800 PWM CTRL
ManufacturerCirrus Logic Inc
SeriesPopguard®
CDB44800 datasheets
 

Specifications of CDB44800

Amplifier TypeClass DOutput Type8-Channel
Voltage - Supply20 V ~ 50 VOperating Temperature-10°C ~ 70°C
Board TypeFully PopulatedUtilized Ic / PartCS44800
Description/functionAudio DSPsOperating Supply Voltage5 V
ProductAudio ModulesFor Use With/related ProductsCS44800
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantMax Output Power X Channels @ Load-
Other names598-1532
CDB-44800
  
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8-Channel Digital Amplifier Controller
Features
> 100 dB Dynamic Range - System Level
< 0.03% THD+N @ 1 W - System Level
32 kHz to 192 kHz Sample Rates
Internal Oscillator Circuit Supports 24.576 MHz
to 54 MHz Crystals
Integrated Sample Rate Converter (SRC)
Eliminates Clock Jitter Effects
Input Sample Rate Independent Operation
Power Supply Rejection Realtime Feedback
Spread Spectrum Modulation - Reduces EMI
®
PWM Popguard
for Single-Ended Mode
PS_SYNC
PWM
XTI
Clock
XTO
Control
SYS_CLK
Auto Fs
DAI_MCLK
Detect
DAI_SCLK
DAI_LRCK
DAI
Serial
DAI_SDIN1
Port
DAI_SDIN2
DAI_SDIN3
DAI_SDIN4
MUTE
SCL/CCLK
SDA/CDOUT
AD1/CDIN
2
SPI/I
C Host
Control Port
AD0/CS
RST
INT
http://www.cirrus.com
Eliminates AM Frequency Interference
Programmable Load Compensation Filters
Support for up to 40 kHz Audio Bandwidth
Digital Volume Control with Soft Ramp
+24 to -127 dB in 0.25 dB Steps
Per Channel Programmable Peak Detect and
Limiter
SPI™ and I²C
Separate 2.5 V to 5.0 V Serial Port and Host
Control Port Supplies
Multibit
Volume
Σ∆
/ Limiter
Modulator
Multibit
Volume
Σ∆
/ Limiter
Modulator
SRC
Multibit
Volume
Σ∆
/ Limiter
Modulator
Multibit
Volume
Σ∆
/ Limiter
Modulator
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
CS44800
®
Host Control Interfaces
PSR_RESET
Power
PSR_EN
Supply
PSR_MCLK
PSR_SYNC
Rejection
PSR_DATA
PWMOUTA1+
PWM
PWMOUTA1-
PWMOUTB1+
Conversion
PWMOUTB1-
PWMOUTA2+
PWM
PWMOUTA2-
PWMOUTB2+
Conversion
PWMOUTB2-
PWMOUTA3+
PWM
PWMOUTA3-
Conversion
PWMOUTB3+
PWMOUTB3-
PWMOUTA4+
PWM
PWMOUTA4-
Conversion
PWMOUTB4+
PWMOUTB4-
GPIO0
GPIO1
PWM
GPIO2
Backend
GPIO3
Control/
GPIO4
Status
GPIO5
GPIO6
MARCH '06
DS632F1

CDB44800 Summary of contents

  • Page 1

    Digital Amplifier Controller Features > 100 dB Dynamic Range - System Level < 0.03% THD System Level 32 kHz to 192 kHz Sample Rates Internal Oscillator Circuit Supports 24.576 MHz to 54 MHz Crystals Integrated ...

  • Page 2

    General Description The CS44800 is a multi-channel digital-to-PWM Class D audio system controller including interpolation, sample rate conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedback in a 64-pin LQFP pack- age.The architecture uses a direct-to-digital approach ...

  • Page 3

    TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 SPECIFIED OPERATING CONDITIONS .............................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8 DC ELECTRICAL CHARACTERISTICS ............................................................................................... 9 DIGITAL INTERFACE CHARACTERISTICS ........................................................................................ 9 PWM OUTPUT PERFORMANCE CHARACTERISTICS .................................................................... 10 PWM FILTER CHARACTERISTICS ................................................................................................... 11 ...

  • Page 4

    Increment (INCR) ................................................................................................................. 50 7.1.2 Memory Address Pointer (MAPx) ......................................................................................... 50 7.2 CS44800 I.D. and Revision Register (address 01h) (Read Only) ................................................. 50 7.2.1 Chip I.D. (Chip_IDx) ............................................................................................................. 50 7.2.2 Chip Revision (Rev_IDx) ...................................................................................................... 50 7.3 Clock Configuration and ...

  • Page 5

    Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0]) ......................................... 63 7.20 Interrupt Mode Control (address 28h) ......................................................................................... 63 7.20.1 Interrupt Pin Control (INT1/INT0) ....................................................................................... 63 7.20.2 Overflow Level/Edge Select (OVFL_L/E) ........................................................................... 64 7.21 Interrupt Mask (address 29h) ...................................................................................................... 64 7.22 ...

  • Page 6

    LIST OF FIGURES Figure 1.Performance Characteristics Evaluation Active Filter Circuit ...................................................... 10 Figure 2.XTI Timings ................................................................................................................................. 11 Figure 3.SYS_CLK Timings ...................................................................................................................... 12 Figure 4.PWMOUTxx Timings .................................................................................................................. 12 Figure 5.PS_SYNC Timings ...................................................................................................................... 12 Figure 6.Serial Audio Interface Timing ...................................................................................................... 13 Figure ...

  • Page 7

    LIST OF TABLES Table 1. Common DAI_MCLK Frequencies .............................................................................................. 25 Table 2. DAI Serial Audio Port Channel Allocations ................................................................................. 27 Table 3. Load Compensation Example Settings ....................................................................................... 32 Table 4. Typical PWM Switch Rate Settings ............................................................................................. 34 Table 5. Digital ...

  • Page 8

    CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25°C.) A SPECIFIED OPERATING CONDITIONS (GND = ...

  • Page 9

    DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to ground; DAI_MCLK = 12.288 MHz, XTAL = 24.576 MHz, PWM Switch Rate = 384 kHz unless otherwise specified.) Parameter Normal Operation (Note 4) Power Supply Current (Note 5) ...

  • Page 10

    PWM OUTPUT PERFORMANCE CHARACTERISTICS (Logic “0” = GND = 0 V; Logic “1” = VLS = VLC 2.5 V; DAI_MCLK = 12.288 MHz; XTAL= 24.576 MHz; PWM Switch Rate = 384 kHz kHz to 192 ...

  • Page 11

    PWM FILTER CHARACTERISTICS (Logic “0” = GND = 0 V; Logic “1” = VLS = VLC 2.5 V; DAI_MCLK = 12.288 MHz; XTAL = 24.576 MHz; PWM Switch Rate = 384 kHz kHz to 192 ...

  • Page 12

    SWITCHING CHARACTERISTICS - SYS_CLK (VD = 2.5 V, VDP = VLC = VDX = 3.3 V, VLS = 2 5.0 V, Cload = 50 pF) Parameter SYS_CLK Period SYS_CLK Duty Cycle SYS_CLK SWITCHING CHARACTERISTICS - PWMOUTA1-B4 (VD = ...

  • Page 13

    SWITCHING CHARACTERISTICS - DAI INTERFACE (VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLS.) Parameters RST pin Low Pulse Width DAI_MCLK ...

  • Page 14

    SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (VD = 2.5 V, VDX = VDP = VLS = 3.3 V; VLC = 2 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C Parameter SCL Clock ...

  • Page 15

    SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C Parameter CCLK Clock Frequency CS ...

  • Page 16

    PIN DESCRIPTIONS GND 1 PSR_EN 2 PS_SYNC 3 GND 4 XTI 5 XTO 6 VDX 7 SYS_CLK 8 DAI_MCLK 9 DAI_SCLK 10 DAI_LRCK ...

  • Page 17

    Power Supply Synchronization Clock (Output) - The PWM synchronized clock to the PS_SYNC 3 switch mode power supply. Crystal Oscillator Input (Input) - Crystal Oscillator input or accepts an external clock XTI 5 input signal that is used to drive ...

  • Page 18

    General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- GPIO2 33 ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller. ...

  • Page 19

    GND 36, 42, Digital Ground (Input) - Ground reference for digital circuits. 48, 53, 59 DS632F1 CS44800 19 ...

  • Page 20

    I/O Pin Characteristics Power Signal Name Rail I/O RST VLC Input SCL/CCLK VLC Input Input / SDA/CDOUT VLC Output AD0/CS VLC Input AD1/CDIN VLC Input INT VLC Output MUTE VLC Input DAI_SDINx VLS Input DAI_SCLK VLS Input DAI_LRCK VLS ...

  • Page 21

    TYPICAL CONNECTION DIAGRAMS +2 0.1 µF 0.01 µF 10 µF 0.1 µF 0.01 µF +3 +5.0 V 0.1 µF 0.01 µF 24.576 MHz XTAL to 54 MHz +2 +5.0 V 0.1 µF 0.01 ...

  • Page 22

    V + 0.1 µF 0.01 µF 10 µF 0.1 µF 0.01 µF +3 +5.0 V 0.01 µF 0.1 µF 24.576 MHz XTAL to 54 MHz +2 +5.0 V 0.1 µF 0.01 µF Digital Audio Processor ...

  • Page 23

    APPLICATIONS 4.1 Overview The CS44800 is a multi-channel digital-to-PWM Class D audio system controller including interpolation, sample rate conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedback in a 64-pin LQFP package. The architecture uses a ...

  • Page 24

    Digital volume control with soft ramp. • Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB steps. • Master volume attenuation; +24 to -127 dB in 0.25 dB steps. • Peak Detect and ...

  • Page 25

    FsIn Domain Clocking Common DAI_MCLK frequencies and sample rates are shown in Mode Sample (sample-rate range) Rate (kHz) DAI_MCLK/LRCK Ratio −> 32 Single Speed ( kHz) 44.1 48 DAI_MCLK/LRCK Ratio −> 64 Double Speed (50 to 100 ...

  • Page 26

    Y1 C3 Appropriate clock dividers for each functional block and a programmable divider to support an output for switched-mode power supply synchronization are provided. The clock generation for the CS44800 is shown in the Figure 16. XTO XTI SYS_CLK PS_SYNC ...

  • Page 27

    FsIn Clock Domain Modules 4.4.1 Digital Audio Input Port The CS44800 interfaces to an external Digital Audio Processor via the Digital Audio Input serial port, the DAI serial port. The DAI port has formats. The DAI port operates in ...

  • Page 28

    I²S Data Format For I²S, data is received most significant bit first, one DAI_SCLK delay after the transition of DAI_LRCK, and is valid on the rising edge of DAI_SCLK. For the I²S format, the left channel data is presented ...

  • Page 29

    Right-Justified Data Format In the right-justified format, data is received most significant bit first and with the least significant bit pre- sented on the last DAI_SCLK before the DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. ...

  • Page 30

    One Line Mode #2 In One Line mode #2 format, data is received most significant bit first on the first DAI_SCLK after a DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a ...

  • Page 31

    Auto Rate Detect The CS44800 will automatically determine the incoming sample rate, DAI_LRCK, to master clock, DAI_MCLK, ratio and configure the appropriate internal clock divider such that the sample rate convertor receives the required clock rate. A minimum DAI_MCLK ...

  • Page 32

    FsOut Clock Domain Modules 4.5.1 Sample Rate Converter One of the characteristics of a PWM amplifier is that the frequency content of out-of-band noise generated by the modulator is dependent on the PWM switching frequency. The power stage external ...

  • Page 33

    SZC[1:0] bits. Each PWM channel output can be independently muted via mute control bits in the register (address 13h)” on page When enabled, ...

  • Page 34

    Fsout (kHz) Fsin (kHz) using SRC 32, 44.1, 48, 88.2, 96, 176.4, 192 32, 44.1, 48, 88.2, 96, 176.4, 192 4.5.6 Interpolation Filter The times 2 (2x) interpolation filter is part of the Quantizer and is used to up sample ...

  • Page 35

    Power Supply Rejection (PSR) Real-Time Feedback Inherent to most Class D power amplifier solutions is the requirement for a clean and well-regulated high voltage power supply. Any noise or tones present on the power rail will couple through each ...

  • Page 36

    Control Port Description and Timing The control port is used to access the registers, allowing the CS44800 to be configured for the desired op- erational modes and formats. The operation of the control port may be completely asynchronous with ...

  • Page 37

    I²C Mode In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There pin. Pins AD0 and AD1 form the two least significant bits ...

  • Page 38

    Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Each byte is separated by an acknowledge bit. 4.6.3 GPIOs The CS44800 GPIO pins will have the following features: • Data direction control. • Programmable ...

  • Page 39

    POWER SUPPLY, GROUNDING, AND PCB LAYOUT The CS44800 requires a 2.5 V digital power supply for the core logic. In order to support a number of PWM backend solutions, separate VDP power pins are provided to condition the interface ...

  • Page 40

    Figure 28 shows the recommended crystal circuit layout the CS44800. C1 and C2 are the VDX power supply decoupling capacitors the crystal and C3, C4, L1 and C5 are the associated components for the crystal circuit. ...

  • Page 41

    Figure 29 shows the recommended PSR circuit layout. See the CS4461 datasheet for further details on the input buffer and other associated external components the CS4461 and U2 is the input buffer op-amp. All supply decoupling should be ...

  • Page 42

    Reset and Power-Up Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, and configuration pins are stable also recommended that the RST pin be activated if the voltage supplies drop ...

  • Page 43

    When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘11’b and the required ramp speed, to initiate a ramp cycle when the channel is powered on. Set MIN_PULSE[4:0] to ‘00000’b. 7. Set the PDN bit ...

  • Page 44

    Done 5.1.4 Recommended Power-Down Sequence 1. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b. 2. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘01’b and the required ramp speed, to initiate ...

  • Page 45

    Set the PDN bit to ‘1’b to put the CS44800 in the power down state. ...

  • Page 46

    REGISTER QUICK REFERENCE Addr Function 7 6 01h ID / Rev. CHIP_ID3 CHIP_ID2 page 50 default 1 1 Clock Config / Power EN_SYS_CLK SYS_CLK_DIV1 02h Control page 51. default 1 0 03h Chnl Power Down PDN_PWMB4 PDN_PWMA4 page 52. ...

  • Page 47

    Addr Function 7 6 Channel Vol. Con- CHB2_FVOL1 CHB2_FVOL0 11h trol 1-Fraction page 59. default 0 0 Channel Vol. Con- CHB4_FVOL1 CHB4_FVOL0 12h trol 2-Fraction page 59 default 0 0 13h Channel Mute CHB4_MUTE CHA4_MUTE page 60 default 0 0 ...

  • Page 48

    Addr Function 7 6 Chnl A3 Comp. RESERVED RESERVED 21h Filter - Fine Adj page 63 default 0 0 Chnl B3 Comp. RESERVED RESERVED 22h Filter - Coarse Adj page 62 default 0 0 Chnl B3 Comp. RESERVED RESERVED 23h ...

  • Page 49

    Addr Function 7 6 PWM Config OSRATE RESERVED 31h page 68 default 0 0 PWM Minimum Pulse DISABLE_ RESERVED 32h Width PWMOUTxx- page 69 default 0 0 33h PWMOUT Delay DIFF_DLY2 DIFF_DLY1 page 70 default 0 0 PSR / Power ...

  • Page 50

    REGISTER DESCRIPTION All registers are read/write except for I.D. and Revision Register, Interrupt Status and Decimator OutD registers which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after ...

  • Page 51

    Clock Configuration and Power Control (address 02h EN_SYS_CLK SYS_CLK_DIV1 SYS_CLK_DIV0 7.3.1 Enable SYS_CLK Output (EN_SYS_CLK) Default = 1 Function: This bit enables the driver for the SYS_CLK signal. If the SYS_CLK output is unused, this bit ...

  • Page 52

    Power Down Output Mode (PDN_OUTPUT_MODE) Default = PWM Outputs are driven low during power down 1 - PWM Outputs are driven to the inactive state during power down Function: This bit is used to select the ...

  • Page 53

    Misc. Configuration (address 04h DIF2 DIF1 DIF0 7.5.1 Digital Interface Format (DIFX) Default = 001 Function: These bits select the digital interface format used for the DAI Serial Port. The required relationship be- tween the Left/Right clock, ...

  • Page 54

    De-Emphasis Control (DEM[1:0]) Default = de-emphasis kHz de-emphasis filter 10 - 44.1 kHz de-emphasis filter kHz de-emphasis filter Function: Enables the appropriate digital filter to maintain the standard 15 ...

  • Page 55

    Volume Control Configuration (address 06h SNGVOL SZC1 SZC0 7.7.1 Single Volume Control (SNGVOL) Default = 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control reg- isters when this function is disabled. ...

  • Page 56

    Soft and Zero Cross bits (SZC[1:0]). This bit does not cause a mute condition to occur. The MUTE_50/50 bit only defines operation during a normal mute condition. When MUTE_50/50 is set and a mute condition occurs, ...

  • Page 57

    Master Volume Control - Integer (address 07h MSTR_IVOL7 MSTR_IVOL6 MSTR_IVOL5 7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0]) Default = 00000000 Function: The Master Volume Control - Integer register allows global control of the signal levels on all ...

  • Page 58

    Convert the decimal integer to binary. This is MSTR_IVOL[7:0]. 2. Select the bit representation of the desired 0.25 fractional increment. This is MSTR_FVOL[1:0]. 3. Concatenate MSTR_IVOL[7:0]: MSTR_FVOL[1:0] to form a 10-bit binary value. 4. Perform a 2’s complement conversion ...

  • Page 59

    Channel XX Volume Control - Integer (addresses 09h - 10h CHXX_IVOL7 CHXX_IVOL6 CHXX_IVOL5 7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0]) Default = 00000000 Function: The Channel X Volume Control - Integer register allows global control of the ...

  • Page 60

    CHXX_IVOL[7:0] 0001 1000 0001 0111 0000 0001 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1110 1111 1101 1000 0010 1000 0001 1000 0001 7.13 Channel Mute (address 13h CHB4_MUTE CHA4_MUTE CHB3_MUTE 7.13.1 Independent Channel ...

  • Page 61

    Peak Limiter Control Register (address 15h RESERVED RESERVED RESERVED 7.15.1 Peak Signal Limit All Channels (LIMIT_ALL) Default = individual channel 1 - all channels Function: When set to 0, the peak signal limiter will ...

  • Page 62

    Binary Code Decimal Value 00000001 00010100 00101000 00111100 01011010 7.17 Limiter Release Rate (address 17h RRATE7 RRATE6 RRATE5 7.17.1 Release Rate (RRATE[7:0]) Default = 00100000 Function: The limiter release rate is user selectable. The effective rate is a ...

  • Page 63

    Table 12. Channel Load Compensation Filter Coarse Adjust 7.19 Chnl XX Load Compensation Filter - Fine Adjust (addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h, 25h, 27h RESERVED RESERVED CHXX_FINE5 7.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0]) Default ...

  • Page 64

    Overflow Level/Edge Select (OVFL_L/E) Default = 0 Function: This bit defines the OVFL interrupt type (0 = level sensitive edge trigger). The Over Flow status of all the audio channels when configured as “edge trigger” is cleared ...

  • Page 65

    SRC Lock Interrupt (SRC_LOCK) Default = 0 Function: When high, indicates that on all active channels, the sample rate converters have achieved lock. This interrupt is an edge-triggered event. If this bit is set to a 1b, indicating a ...

  • Page 66

    Channel Over Flow Status (address 2Bh) (Read Only CHB4_OVFL CHA4_OVFL CHB3_OVFL For all bits in this register, a ‘1’ means the associated condition has occurred at least once since the register was last read. A ‘0’ means ...

  • Page 67

    GPIO Pin Level/Edge Trigger (address 2Eh RESERVED GPIO6_L/E GPIO5_L/E 7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E) Default = 0 Function: General Purpose Input - This bit defines the GPIO input type (0 = level sensitive edge ...

  • Page 68

    GPIO Interrupt Mask Register (address 30h RESERVED RESERVED RESERVED 7.28.1 GPIO Pin Interrupt Mask (M_GPIOX) Default = 0 Function: General Purpose Input - The bits of this register serve as a mask for GPIO[3:0] interrupt sources. If ...

  • Page 69

    PDN bit in the register on page 1b. Attempts to write this register while the PDN is not set will be ignored. 7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG) Default = 0 0 ...

  • Page 70

    PDN bit in the register page 1b. Attempts to write this register while the PDN is not set will be ignored. 7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0]) Default = 00000 Function: The ...

  • Page 71

    The Channel Delay bits allow delay adjustment of each of the PWMOUT differential signal pairs, PW- MOUTAx+/PWMOUTAx- from the associated PWMOUTBx+/PWMOUTBx-. The value of this register de- termines the amount of delay inserted in the output path. The effective delay ...

  • Page 72

    PWMOUTA1+ PWMOUTA1- PWMOUTB1+ PWMOUTB1- PWMOUTA2+ PWMOUTA2- PWMOUTB2+ PWMOUTB2- PWMOUTA3+ PWMOUTA3- PWMOUTB3+ PWMOUTB3- PWMOUTA4+ PWMOUTA4- PWMOUTB4+ PWMOUTB4- 72 tdif dly tch dly tdif dly tdif dly tch dly tdif dly tdif dly tch dly tdif dly tdif dly tch dly tdif ...

  • Page 73

    PSR and Power Supply Configuration (address 34h PSR_EN PSR_RESET FEEDBACK_EN 7.32.1 Power Supply Rejection Enable (PSR_EN) Default = disable 1 - enable Function: Enables the on-card and internal power supply rejection circuitry. This ...

  • Page 74

    Power Supply Rejection Reset (PSR_RESET) Default = force reset condition 1 - remove reset condition Function: This bit is used to assert a reset condition to the on-card PSR components. When set to a ‘0’b, the ...

  • Page 75

    Decimator Scale (DEC_SCALE[18:0]) Default = 25868h Function: These bits are used to scale the power supply reading ing the PSR feedback calibration sequence. DEC_SCALE[18:0] has 19-bit precision, formatted as signed 1.18 with decimal values from -1 to 1-2^(-18). The ...

  • Page 76

    PARAMETER DEFINITIONS Dynamic Range (DR) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth, typically kHz. Dynamic Range is a signal-to-noise ratio ...

  • Page 77

    Signal to Noise Ratio (SNR) SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor, in the presence of a signal measured over ...

  • Page 78

    DIMENSIONS 64L LQFP PACKAGE DRAWING D D1 ∝ L DIM MIN A --- A1 0.002 B 0.007 D 0.461 D1 0.390 E 0.461 E1 0.390 e* 0.016 L 0.018 ∝ 0.000° * Nominal pin pitch is 0.50 mmControlling dimension ...

  • Page 79

    ... Figure 12. Typical Half-Bridge Connection Diagram on page 22 Figure 13 on page 24 Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 53 “Ordering Information” on page 79 CS44800 Min Typ Max Units - 48 - °C/Watt - 38 - Order# Rail CS44800-CQZ Tape and CS44800-CQZR Reel Rail CS44800-DQZ Tape and CS44800-DQZR Reel - - CDB44800 - - CRD44800 - - CRD44800-ST- CRD44600-PH-FB 79 ...

  • Page 80

    Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in ...