CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 33

• Manufacturer Part Number: CDB44800
• Description: BOARD EVAL FOR CS44800 PWM CTRL
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB44800

• Amplifier Type: Class D
• Output Type: 8-Channel
• Voltage - Supply: 20 V ~ 50 V
• Operating Temperature: -10°C ~ 70°C
• Board Type: Fully Populated
• Utilized Ic / Part: CS44800
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS44800
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Max Output Power X Channels @ Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1532; CDB-44800

DS632F1
4.5.4
4.5.5
Features:
• Up to
• 64 Quantization levels
• PSRR compensation feedback
• Programmable Over Sampling - interpolate times 2 (2x) or filter by-pass. By-pass is intended for
• Programmable registers to move PWM edges for delay adjustment. This lowers the overall noise con-
• Programmable Modulation Setup
ger (addresses 09h - 10h)” on page
of 0.125 dB at a variable rate controlled by the SZC[1:0] bits.
Each PWM channel output can be independently muted via mute control bits in the register
(address 13h)” on page
When enabled, each CHXX_MUTE bit attenuates the corresponding PWM channel to its maximum value
(-127 dB). When the CHXX_MUTE bit is disabled, the corresponding PWM channel returns to the atten-
uation level set in the Volume Control register. The attenuation is ramped up and down at the rate spec-
ified by the SZC[1:0] bits.
Peak Detect / Limiter
The CS44800 has the ability to limit the maximum signal amplitude to prevent clipping. The
Control Register (address 15h)” on page 60
eration. Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the
iter Attack Rate (address 16h)” on page
(address 17h)” on page
PWM Engines
There are
Each PWM can handle one stereo pair and connects to a driver or a pair of drivers, depending on the
output configuration. Each PWM Engine receives the master clock, PWM_MCLK, from the Clock Control
block, and the associated channel data and audio sample timings from the Sample Rate Converter.
The
eration. This register controls the parameters of the PWM engines and can only be changed while the
PWM engines are in the power down state.
The table below shows the available settings for the PWM Engine for a 384 kHz/768 kHz or
421.875 kHz/843.75 kHz PWM Fswitch rate verses the supported Fsin sample rates using the SRC with
a maximum PWM_MCLK of 49.152 MHz/54 MHz.
384 kHz (single-speed) PWM switch rate support. The interpolate 2x filter is used to upsample the data
to support a PWM switch rate of 768 kHz (double speed mode). This enables the output frequency re-
sponse to extend past 20 kHz when the DAI sample rate is 96 kHz or 192 kHz.
tribution by allowing each PWM edge to switch at different times.
– Min/Max PWM pulse width allowed
– Programmable Modulation index.
“PWM Configuration Register (address 31h)” on page 68
8
channel support
four
stereo PWM Engines: PWM_ENG_1, PWM_ENG_2, PWM_ENG_3 and PWM_ENG_4.
60.
61.
58. Volume control changes are programmable to ramp in increments
61. The release rate is determined by the
is used to configure the peak detect and limiter engines’ op-
is used to configure the PWM engines’ op-
“Limiter Release Rate
“Channel Mute
“Peak Limiter
CS44800
“Lim-
33