CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 34

• Manufacturer Part Number: CDB44800
• Description: BOARD EVAL FOR CS44800 PWM CTRL
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB44800

• Amplifier Type: Class D
• Output Type: 8-Channel
• Voltage - Supply: 20 V ~ 50 V
• Operating Temperature: -10°C ~ 70°C
• Board Type: Fully Populated
• Utilized Ic / Part: CS44800
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS44800
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Max Output Power X Channels @ Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1532; CDB-44800

34
4.5.6
4.5.7
4.5.8
4.5.9
32, 44.1, 48, 88.2, 96,
32, 44.1, 48, 88.2, 96,
Interpolation Filter
The times 2 (2x) interpolation filter is part of the Quantizer and is used to up sample the data to support
a higher PWM switch rate. The interpolator is controlled by the OSRATE bit in the
Register (address 31h)” on page 68
Quantizer
The quantizer takes the input audio data at a typical 384 kHz or 768 kHz rate (depending on whether the
2x Interpolator is on or not) from the Interpolator as input. When PSRR is enabled, the quantizer takes the
input from PSRR Decimator and uses it to correct for power_supply noise. It also provides protection
through min/max pulse limiting hardware to generate outputs that wouldn’t violate minimum pulse widths
required at the PWM drivers. Its stereo outputs are running at the PWM switch rate.
Modulator
Each output from the Quantizer goes to the Modulator. The Modulator takes the parallel input data at a
384 kHz or 768 kHz, depending on the setting of the OSRATE bit, and changes the parallel data to serial,
one-bit outputs. The result is modulated pulses at the selected switch rate with 64 level resolution. The
modulator maintains low frequency audio signals, allowing the output to reproduce all low frequency audio
content down to 0 Hz.
PWM Outputs
The Modulators outputs are followed by the PWM Configuration block. These signals are routed through
delay control blocks where they generate two outputs each. These final outputs are modulated pulses run-
ning at the PWM switch rate as determined by the settings shown in
Circuitry in the PWM Configuration block guarantees, that no pulses shorter than the minimum pulse are
generated. The minimum pulse width is configured using the MIN_PULSE[4:0] bits in the
Pulse Width Register (address 32h)” on page
The PWM Configuration block also provides the PWM output signal delay mechanism. Adjusting the out-
puts’ delays allows for managing the switching noise between channels, as well as differential signal
noise. The
Output. The delay is measured in periods of PWM_MCLK.
Fsin (kHz)
176.4, 192
176.4, 192
“PWMOUT Delay Register (address 33h)” on page 70
Fsout (kHz)
using SRC
421.875
Table 4. Typical PWM Switch Rate Settings
384
and employs digital filtering to provide high quality interpolation.
Quant Level
64
64
64
64
69.
OSRATE
1
2
1
2
specify the delay amount for each PWM
Switch Rate
421.875
843.75
Table
PWM
(kHz)
384
768
4.
Required XTAL
or SYS_CLK
“PWM Configuration
24.576
49.152
27.000
54.000
(MHz)
“PWM Minimum
CS44800
DS632F1