CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 37

• Manufacturer Part Number: CDB44800
• Description: BOARD EVAL FOR CS44800 PWM CTRL
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB44800

• Amplifier Type: Class D
• Output Type: 8-Channel
• Voltage - Supply: 20 V ~ 50 V
• Operating Temperature: -10°C ~ 70°C
• Board Type: Fully Populated
• Utilized Ic / Part: CS44800
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS44800
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Max Output Power X Channels @ Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1532; CDB-44800

DS632F1
4.6.2
SCL
SDA
SDA
SCL
I²C Mode
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should
be connected through a resistor to VLC or GND as desired. The state of the pins is sensed while the
CS44800 is being reset.
The signal timings for a read and write cycle are shown in
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS44800 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low
for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS44800,
the chip address field, which is the first byte sent to the CS44800, should match 10011 followed by the
settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the op-
eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto incre-
ment bit in MAP allows successive writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS44800 after each input byte is read, and is input to the
CS44800 from the microcontroller after each transmitted byte. Autoincrement reads are not supported.
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As
shown in Figure 26, the write operation is aborted after the acknowledge for the MAP byte by sending a
stop condition. The following pseudocode illustrates an aborted write operation followed by a read oper-
ation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
START
START
0
1
CHIP ADDRESS (WRITE)
0
1
1
0
CHIP ADDRESS (WRITE)
1
0
2
0
1
0
3
2
1 AD1 AD0 0
1
4
3
1 AD1 AD0 0
5
4
6
5
Figure 25. Control Port Timing, I²C Slave Mode Write
Figure 26. Control Port Timing, I²C Slave Mode Read
7
6
ACK
8
7
9
INCR
ACK
8
10 11
6
INCR
9
5
MAP BYTE
12 13 14 15
10 11
6
4
MAP BYTE
5
3
12
4
2
13 14 15
1
3
16
0
2
ACK
STOP
17 18
1
START
16 17 18
0
ACK
19
1
20 21 22 23 24
CHIP ADDRESS (READ)
0
7
0
19
6
DATA
1
Figure 25
1 AD1 AD0 1
24 25
1
0
ACK
25
26
26 27 28
27 28
7
ACK
and
DATA +1
6
7
DATA
Figure
1
0
ACK
0
DATA +1
7
7
26. A Start condition is
DATA +n
6
0
1
DATA + n
7
0
ACK
0
STOP
CS44800
ACK
NO
STOP
37