CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 43

• Manufacturer Part Number: CDB44800
• Description: BOARD EVAL FOR CS44800 PWM CTRL
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB44800

• Amplifier Type: Class D
• Output Type: 8-Channel
• Voltage - Supply: 20 V ~ 50 V
• Operating Temperature: -10°C ~ 70°C
• Board Type: Fully Populated
• Utilized Ic / Part: CS44800
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS44800
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Max Output Power X Channels @ Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1532; CDB-44800

DS632F1
5.1.3
6. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘11’b and
7. Set the PDN bit to ‘0’b to take the CS44800 out of the power-down state.
8. Start all clocks on the DAI interface (DAI_MCLK, DAI_SCLK, DAI_LRCK). This will initiate the SRC to
9. Wait for the SRC to lock.
10. If using the PSR feedback, jump to
11. Set the appropriate GPIO pin, or other control signal, to enable the power output stage.
12. Enable each channel’s PWM modulator by setting the PDN_PWMxx bit to ‘0’b. If full-bridged, go to
13. Wait for the ramp-up sequence to complete. The ramp-up function can be configured to cause an
14. For full-bridged power output stage configurations, the ramp-up sequence is not required. Enabling
15. If using the PSR feedback, set the FEEDBACK_EN bit to ‘1’b.
16. Un-mute all active channels.
17. At this point, the CS44800 is ready to accept audio samples and begin playback.
1. Set the DEC_SHIFT[2:0]/DEC_SCALE[18:0] coefficient (C
2. Set the PSR_RESET bit to ‘1’b.
3. Set the PSR_EN bit to ‘1’b.
4. Set the PSR_EN bit to ‘0’b.
5. Read DEC_OUTD[23:0].
6. See
7. Continue Recommended Power-Up Sequence.
Recommended PSR Calibration Sequence
the required ramp speed, to initiate a ramp cycle when the channel is powered on. Set
MIN_PULSE[4:0] to ‘00000’b.
begin the lock sequence. The SRC lock function can be configured to cause an interrupt condition
when lock has been completed. This will be indicated by an active INT signal.
finished, continue to step 12. If not using PSR feedback, continue to step 12.
step 14. If single-ended (half-bridged), this will initiate a sequence which will slowly increase the DC
voltage, from 0V to Vpower÷2, across the AC coupling capacitor. This will eliminate the instantaneous
charge across the capacitor which would have caused an audible pop from the speaker.
interrupt condition when the ramp period has completed. This will be indicated by an active INT signal.
Once the ramp-up sequence has completed, set the RAMP[1:0] bits to ‘01’b
the power output stage will not cause an audible pop from the speaker.
36h = 00h, 37h = 00h).
Figure 30
to adjust the DEC_SHIFT[2:0]/DEC_SCALE[18:0] registers.
“Recommended PSR Calibration Sequence” on page
PSR
) to decimal 1.0 (register 35h = 22h,
CS44800
44. When
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