CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 61

• Manufacturer Part Number: CDB44800
• Description: BOARD EVAL FOR CS44800 PWM CTRL
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB44800

• Amplifier Type: Class D
• Output Type: 8-Channel
• Voltage - Supply: 20 V ~ 50 V
• Operating Temperature: -10°C ~ 70°C
• Board Type: Fully Populated
• Utilized Ic / Part: CS44800
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS44800
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Max Output Power X Channels @ Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1532; CDB-44800

DS632F1
7.15
7.15.1 Peak Signal Limit All Channels (LIMIT_ALL)
7.15.2 Peak Signal Limiter Enable (LIMIT_EN)
7.16
7.16.1 Attack Rate (ARATE[7:0])
RESERVED
ARATE7
7
7
Peak Limiter Control Register (address 15h)
Limiter Attack Rate (address 16h)
Default = 0
0 - individual channel
1 - all channels
Function:
When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the
specific channel indicating clipping. The other channels will not be affected.
When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on ALL
channels in response to ANY single channel indicating clipping.
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS44800 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the Limiter At-
tack Rate register.
Default = 00010000
Function:
The limiter attack rate is user selectable. The effective rate is a function of the SRC output sampling fre-
quency and the value in the Limiter Attack Rate register. Rates are calculated using the function
RATE = (32/{value})/SRC Fs, where {value} is the decimal value in the Limiter Attack Rate register and
SRC Fs is the output sample rate of the SRC which is determined by the PWM master clock frequency.
SRC Fs equals 384 kHz for 24.576 MHz based clocks and 421.875 kHz for 27.000 MHz based clocks.
Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see
RESERVED
ARATE6
6
6
RESERVED
ARATE5
5
5
RESERVED
ARATE4
4
4
RESERVED
ARATE3
3
3
Peak Limiter Control Register (address
RESERVED
ARATE2
2
2
LIMIT_ALL
ARATE1
1
1
CS44800
LIMIT_EN
ARATE0
15h)).
0
0
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