SI3460-EVB Silicon Laboratories Inc, SI3460-EVB Datasheet

BOARD EVAL POE FOR SI3460

SI3460-EVB

Manufacturer Part Number
SI3460-EVB
Description
BOARD EVAL POE FOR SI3460
Manufacturer
Silicon Laboratories Inc
Type
DC/DC Switching Converters, Regulators & Controllersr
Datasheets

Specifications of SI3460-EVB

Main Purpose
Special Purpose DC/DC, Power Over Ethernet
Outputs And Type
1, Non-Isolated
Voltage - Output
-48V
Board Type
Fully Populated
Utilized Ic / Part
Si3460
Input Voltage
12 V, 15 V
Output Voltage
- 48 V
Interface Type
Ethernet
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Product
Power Management Modules
For Use With/related Products
Si3460
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output
-
Voltage - Input
-
Power - Output
-
Frequency - Switching
-
Regulator Topology
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1842
I E E E 8 0 2 . 3 a f P S E I
Features
Applications
Description
The Si3460 is a single-port, –48 V power management controller for
IEEE 802.3af-compliant Power Sourcing Equipment (PSE). Designed
to minimize system cost and ease implementation in embedded PSE
endpoint (switches) or midspan (power injector) applications, the
Si3460 operates directly from a 12 or 15 V input supply and integrates
a digital PWM-based dc-dc converter for generating the –48 V PSE
output supply. The IEEE-required Powered Device (PD) detection
feature uses a robust 3-point algorithm to avoid false detection events.
The Si3460's reference design kit also provides full IEEE-compliant
classification and PD disconnect. Intelligent protection circuitry
includes input undervoltage lockout (UVLO), classification-based
current limiting, and output short-circuit protection. The Si3460 is
designed to operate completely independently of host processor
control. An LED status signal is provided to indicate the port status,
including detect, power good, and output fault event information for
use within the host system. The Si3460 is pin-programmable to
support endpoint and midspan applications as well as each of the
different classification power levels specified by the IEEE 802.3af
standard. A comprehensive reference design kit is available (Si3460-
EVB), including a complete schematic and BOM (Bill-of-Materials) for
the dc-dc converter and PSE functions.
Rev. 1.1 6/10
IEEE 802.3af™ compliant PSE and
dc-dc controller
Autonomous operation requires no
host processor interface
Complete reference design
available, including Si3460 controller,
PSE firmware, and schematic:




IEEE 802.3af endpoints and
midspans
Environment A and B PSEs
Embedded PSEs
DC-DC controller generates –48 V
footprint
+15 V isolated supply
PSE output for SELV compatibility
with telephony interfaces
output power (Class 0)
Low-cost BOM with compact PCB
Operates directly from a +12 or
Supports up to 15.4 W maximum
Copyright © 2010 by Silicon Laboratories






UNH Interoperability Test Lab test
report available
Extended operating range
(–40 to +85 °C)
11-Pin Quad Flat No-Lead (QFN)

Set-top boxes
FTTH media converters
Cable modem and DSL
gateways
N T E R F A C E A N D
Robust 3-point detection
algorithm eliminates false
detection events
IEEE-compliant classification
IEEE-compliant disconnect
Inrush current control
Short-circuit output fault
protection
LED status signal (detect,
power good, output fault)
Tiny 3 x 3 mm PCB footprint;
Pb-free, RoHS-compliant
D C - D C C
250KHZ
CTRL1
CTRL2
GATE
VDD
Top View—Pads on bottom of package
1
2
3
4
5
Pin Assignments
11-pin QFN (3x3 mm)
O N T R O L L E R
Si3460
GND
S i 3 4 6 0
10
9
8
7
6
STATUS
ISENSE
RST
VSENSE
DETA
Si3460

Related parts for SI3460-EVB

SI3460-EVB Summary of contents

Page 1

... IEEE 802.3af-compliant Power Sourcing Equipment (PSE). Designed to minimize system cost and ease implementation in embedded PSE endpoint (switches) or midspan (power injector) applications, the Si3460 operates directly from input supply and integrates a digital PWM-based dc-dc converter for generating the –48 V PSE output supply. The IEEE-required Powered Device (PD) detection feature uses a robust 3-point algorithm to avoid false detection events ...

Page 2

... Si3460 Block Diagram OTP Memory Machine RST STATUS 2 PWM DC/DC Osc. Controller: UVLO, Current Limiting, State Short Circuit Protection Control Config. PSE & LED Controller: I/F Detection Classification Disconnect Rev. 1.1 GATE 250KHZ VSENSE ISENSE CTRL1 CTRL2 DETA ...

Page 3

... ABLE O F ONTENTS Section 1. Si3460-EVB Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. Si3460-EVB Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. Si3460 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. Si3460-EVB Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1. PSE Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. DC-DC Converter Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4. Si3460-EVB Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. Operating Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3. Operating Mode Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 ...

Page 4

... Si3460 1. Si3460-EVB Application Diagram V IN RST +11V to 16V V EE Note: Refer to the Si3460-EVB User Guide for complete schematic details Figure 1. Si3460-EVB Application Diagram 4 VDD ISENSE GATE CTRL1 DETA Si3460 PWM BOM 250KHZ CTRL2 VSENSE STATUS GND DETECT FAULT PGOOD Rev. 1.1 ...

Page 5

... When implemented according to the recommended external components and layout guidelines for the Si3460- EVB, the Si3460 enables the following performance specifications in single-port PSE applications. Please refer to the Si3460-EVB User’s Guide and schematics for details. Table 1. Selected Electrical Specifications (Si3460-EVB) Symbol ...

Page 6

... Si3460 2. Si3460 Electrical Specifications The following specifications apply to the Si3460 controller. Refer to Tables and 7, the Si3460-EVB User’s Guide, and schematics for additional details about the electrical specifications of the Si3460-EVB reference design. Table 2. Recommended Operating Conditions* Symbol Description Operating temperature range ...

Page 7

... µA — — 0.4 x VDD OL Any digital pin 0.7 x VDD Any digital pin — — IN — — Rev. 1.1 Si3460 Typ Max Unit — — — — V — — 0.6 — 0.1 V — V — 0.3 x VDD V ±1 — µA 5 — ...

Page 8

... Si3460-EVB Performance Characteristics When implemented in accordance with the recommended external components and layout guidelines, the Si3460 controller enables the following typical performance characteristics in single-port PSE applications. Refer to the Si3460-EVB applications note, schematics, and user's guide for more details. Table 5. PSE Performance Characteristics Symbol ...

Page 9

... PSE Timing Characteristics When implemented in accordance with the recommended external components and layout guidelines, the Si3460 controller enables the following typical performance characteristics in single-port PSE applications. Refer to the Si3460-EVB applications note, schematics, and user's guide for more details. Table 6. PSE Timing* Symbol ...

Page 10

... DC-DC Converter Performance Characteristics The dc-dc converter utilizes a digital control loop architecture operating at 250 kHz. The complete converter is comprised of the Si3460 controller and the external components in the Si3460-EVB schematics. The performance specifications in Table 7 are typical for the Si3460-EVB reference design. ...

Page 11

... PoE applications. Included in the Si3460-EVB reference design is a digital PWM controller-based dc-dc converter that simplifies overall system design by generating the –48 V PSE supply voltage. An isolated input dc supply is all that is needed to supply the Si3460-EVB reference design. Refer to the Si3460-EVB User’s Guide and schematics for descriptions in the following sections. ...

Page 12

... To eliminate the possibility of false detection events, the Si3460-EVB reference design performs a robust 3-point detection sequence by varying the voltage across the sense bridge R1, R2, and R3. The fourth leg of the sense bridge is the load that connects to the drain of M2 and returns to V via D8 and L1 ...

Page 13

... UVLO The Si3460-EVB reference design is optimized for nominal input voltages (11 V min maximum). If the input voltage drops below detection mode or if the output voltage drops below classification or powerup mode, a UVLO condition is declared, which generates the error condition (LED flashing rapidly). An undervoltage event is a fault condition reported through the status LED as a rapid blinking of 10 flashes per second ...

Page 14

... The input power supply should be rated for at least 25% higher power level than the output power level chosen. This is primarily to account for the 75 to 80% nominal efficiency performance of the Si3460-EVB reference design. For example, to support a Class 0 PSE, for example, the input supply should be capable of supplying 19.25 W (15 ...

Page 15

... Si3460-EVB User’s Guide describes the inputs and outputs of the evaluation system. The electrical characteristics of the Si3460-EVB are summarized in Table 1 on page 5. Refer to the complete Si3460-EVB schematics and BOM listing for information about the external components needed for the complete PSE and dc-dc controller application circuit ...

Page 16

... LED, which indicates when a detect, power good, or output fault condition has occurred. A logic low turns the LED on, and logic high turns the LED off. Ground connection for the Si3460. This is NOT earth ground. Refer to the Si3460-EVB schematics for more information. Rev. 1.1 signature is detected, GOOD ...

Page 17

... Si3460-E03-GM 0.6.8 Si3460-EVB N/A Notes: 1. Add “R” to part number to denote tape-and-reel option (e.g., Si3460-E03-GMR). 2. The ordering part number above is not the same as the device mark. See"8.3. Device Marking of Production Devices" on page 21 for more information. ...

Page 18

... Si3460 8. Package Outline: 11-Pin QFN Figure 4 illustrates the package details for the Si3460. Table 11 lists the values for the dimensions shown in the illustration. The Si3460 is packaged in an industry-standard, 3x3 mm, RoHS-compliant, Pb-free, 11-pin QFN package. Table 11. Package Diagram Dimensions Dimension aaa bbb ...

Page 19

... Solder Paste Mask 0.10 mm 0.35 mm 0.50 mm 0. 0.50 mm 0.35 mm 0. 0.60 mm 0. Figure 5. Solder Paste Mask Rev. 1.1 Si3460 0. ...

Page 20

... Si3460 8.2. PCB Landing Pattern 0.10 mm 0.35 mm 0.50 mm 0. Figure 6. Typical QFN-11 Landing Diagram 0. Rev. 1.1 ...

Page 21

... Line 1 is the part number, line 2 is the lot code, and line 3 is the date code. The part number marking is different for Si3460-E02 devices and Si3460-E03. The silicon revision letter is the first letter of the lot code ("E" for both Si3460- E02 and Si3460-E03 devices). Figure 8 shows how to decode the top side marking. ...

Page 22

... Si3460 OCUMENT HANGE IST Revision 0.4 to Revision 1.0  Added Table 1 specification values on page 5.  Updated Table 5 specification values for I on page 8.  Revised “4.3.2. Classification” text description on page 12.  Added I and I current limits to Table 9 on CUT LIM page 12. ...

Page 23

... N : OTES Rev. 1.1 Si3460 23 ...

Page 24

... Si3460 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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