ISL6526EVAL2

Manufacturer Part NumberISL6526EVAL2
DescriptionEVALUATION BOARD QFN ISL6526
ManufacturerIntersil
ISL6526EVAL2 datasheet
 


Specifications of ISL6526EVAL2

Main PurposeDC/DC, Step DownOutputs And Type1, Non-Isolated
Voltage - Output2.5VCurrent - Output5A
Voltage - Input3.3 ~ 5VRegulator TopologyBuck
Frequency - Switching300kHzBoard TypeFully Populated
Utilized Ic / PartISL6526Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Power - Output-  
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Electrical Specifications
Recommended Operating Conditions, unless otherwise noted V
PARAMETER
GATE DRIVERS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
PROTECTION/DISABLE
OCSET Current Source
Disable Threshold
NOTE:
4. Limits should be considered typical and are not production tested.
Functional Pin Description
14 LD SOIC
TOP VIEW
GND
1
LGATE
2
3
CPVOUT
4
CT1
CT2
5
OCSET
6
FB
7
16 LD 5X5 QFN
TOP VIEW
16
15
14
13
CPVOUT
1
CT1
2
3
CT2
OCSET
4
5
6
7
8
VCC
This pin provides the bias supply for the ISL6526, ISL6526A.
Connect a well-decoupled 3.3V supply to this pin.
COMP and FB
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the internal
error amplifier and the COMP pin is the error amplifier
output. These pins are used to compensate the voltage
control feedback loop of the converter.
6
ISL6526, ISL6526A
SYMBOL
TEST CONDITIONS
I
V
- V
= 5V, V
UGATE-SRC
BOOT
PHASE
UGATE
I
UGATE-SNK
I
V
= 3.3V, V
= 4V
LGATE-SRC
VCC
LGATE
I
LGATE-SNK
I
Commercial
OCSET
Industrial
V
DISABLE
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
14
UGATE
PHASE
BOOT
13
Connect this pin to the upper MOSFET’s source. This pin is
12
PHASE
used to monitor the voltage drop across the upper MOSFET
11
VCC
for overcurrent protection.
10
CPGND
9
ENABLE
UGATE
8
COMP
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the
upper MOSFET has turned off.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
12
PHASE
voltage suitable to drive a logic-level N-Channel MOSFET.
11
VCC
LGATE
10
CPGND
Connect this pin to the lower MOSFET’s gate. This pin provides
the PWM-controlled gate drive for the lower MOSFET. This pin
9
NC
is also monitored by the adaptive shoot-through protection
circuitry to determine when the lower MOSFET has turned off.
OCSET
Connect a resistor (R
upper MOSFET (V
source (I
(r
DS(ON)
according Equation 1:
I
PEAK
An overcurrent trip cycles the soft-start function.
= 3.3V ±5% and T
= +25°C. (Continued)
CC
A
MIN
TYP
MAX
= 4V
-
-1
-
-
1
-
-
-1
-
-
2
-
18
20
22
16
20
22
-
-
0.8
) from this pin to the drain of the
OCSET
). R
, an internal 20µA current
IN
OCSET
), and the upper MOSFET ON-resistance
OCSET
) set the converter overcurrent (OC) trip point
I
xR
OCSET
OCSET
-------------------------------------------------
=
r
(
)
DS ON
UNITS
A
A
A
A
µA
µA
V
(EQ. 1)
FN9055.10
November 24, 2008