ISL6551EVAL1

Manufacturer Part NumberISL6551EVAL1
DescriptionEVALUATION BOARD ISL6551
ManufacturerIntersil
ISL6551EVAL1 datasheets
 


Specifications of ISL6551EVAL1

Main PurposeDC/DC, Step DownOutputs And Type1, Isolated
Voltage - Output3.3VCurrent - Output60A
Voltage - Input36 ~ 75VRegulator TopologyBuck
Frequency - Switching470kHzBoard TypeFully Populated
Utilized Ic / PartISL6551Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Power - Output-  
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Data Sheet
ZVS Full Bridge PWM Controller
The ISL6551 is a zero voltage switching (ZVS) full-bridge
PWM controller designed for isolated power systems. This
part implements a unique control algorithm for fixed-
frequency ZVS current mode control, yielding high efficiency
with low EMI. The two lower drivers are PWM-controlled on
the trailing edge and employ resonant delay while the two
upper drivers are driven at a fixed 50% duty cycle.
This IC integrates many features in both 6x6 mm
28-lead SOIC packages to yield a complete and
sophisticated power supply solution. Control features include
programmable soft-start for controlled start-up,
programmable resonant delay for zero voltage switching,
programmable leading edge blanking to prevent false
triggering of the PWM comparator due to the leading edge
spike of the current ramp, adjustable ramp for slope
compensation, drive signals for implementing synchronous
rectification in high output current, ultra high efficiency
applications, and current share support for paralleling up to
10 units, which helps achieve higher reliability and
availability as well as better thermal management. Protective
features include adjustable cycle-by-cycle peak current
limiting for overcurrent protection, fast short-circuit protection
(in hiccup mode), a latching shutdown input to turn off the IC
completely on output overvoltage conditions or other
extreme and undesirable faults, a non-latching enable input
to accept an enable command when monitoring the input
voltage and thermal condition of a converter, and VDD under
voltage lockout with hysteresis. Additionally, the ISL6551
includes high current high-side and low-side totem-pole
drivers to avoid additional external drivers for moderate gate
capacitance (up to 1.6nF at 1MHz) applications, an
uncommitted high bandwidth (10MHz) error amplifier for
feedback loop compensation, a precision bandgap reference
with ±1.5% (ISL6551AB) or ±1% (ISL6551IB) tolerance over
recommended operating conditions, and a ±5% “in
regulation” monitor.
In addition to the ISL6551, other external elements such as
transformers, pulse transformers, capacitors, inductors and
Schottky or synchronous rectifiers are required for a
complete power supply solution. A detailed 200W telecom
power supply reference design using the ISL6551 with
companion Intersil ICs, Supervisor And Monitor ISL6550 and
Half-bridge Driver HIP2100, is presented in Application Note
AN1002.
In addition, the ISL6551 can also be designed in push-pull
converters using all of the features except the two upper
drivers and adjustable resonant delay features.
1
January 3, 2006
Features
• High Speed PWM (up to 1MHz) for ZVS Full Bridge
Control
• Current Mode Control Compatible
• High Current High-Side and Low-Side Totem-Pole Drivers
• Adjustable Resonant Delay for ZVS
• 10MHz Error Amplifier Bandwidth
2
QFN and
• Programmable Soft-Start
• Precision Bandgap Reference
• Latching Shutdown Input
• Non-latching Enable Input
• Adjustable Leading Edge Blanking
• Adjustable Dead Time Control
• Adjustable Ramp for Slope Compensation
• Fast Short-Circuit Protection (Hiccup Mode)
• Adjustable Cycle-by-Cycle Peak Current Limiting
• Drive Signals to Implement Synchronous Rectification
• VDD Under-voltage Lockout
• Current Share Support
• ±5% “In Regulation” Indication
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Full-Bridge and Push-Pull Converters
• Power Supplies for Off-line and Telecom/Datacom
• Power Supplies for High End Microprocessors and
Servers
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
1-888-INTERSIL or 1-888-468-3774
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6551
FN9066.5

ISL6551EVAL1 Summary of contents

  • Page 1

    ... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003-2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL6551 ...

  • Page 2

    ... Ordering Information PKG. PART DWG. # NUMBER M28.3 ISL6551EVAL1 Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free L28.6x6 material sets; molding compounds/die attach materials and 100% L28.6x6 matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

  • Page 3

    Functional Pin Description PACKAGE PIN # SOIC QFN PIN SYMBOL 1 26 VSS R_RESDLY 5 2 R_RA 6 3 ISENSE 7 4 PKILIM 8 5 BGREF 9 6 R_LEB 10 7 CS_COMP ...

  • Page 4

    Functional Block Diagram BANDGAP REFERENCE BGREF 8 7 PKILIM R_LEB 9 RESODLY RESODLY R_RESDLY 4 ISENSE 6 RAMP RAMP ADJUST ADJUST R_RA CLOCK 3 RD GENERATOR ERROR AMP (See Fig. 4) EAO 14 13 EAI DC OK ...

  • Page 5

    Absolute Maximum Ratings Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . . -0.3 to 16V Enable Inputs (ON/OFF, LATSD ...

  • Page 6

    Electrical Specifications These specifications apply for VDD = VDDP = 12V and T (ISL6551AB), Unless Otherwise Stated (Continued) PARAMETER SYMBOL PWM DELAYS (Note 4) LOW1,2 delay “Rising” LOW1,2 delay “Falling” SYNC1,2 delay “Falling” SYNCF SYNC1,2 delay “Rising” SYNCR ERROR AMPLIFIER ...

  • Page 7

    Electrical Specifications These specifications apply for VDD = VDDP = 12V and T (ISL6551AB), Unless Otherwise Stated (Continued) PARAMETER SYMBOL Vsat_sinking (ISL6551IB) Vsat_low Vsat_sinking (ISL6551AB) Vsat_low SYNCHRONOUS SIGNALS (SYNC1, SYNC2) Maximum capacitive load (each) PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 4) ...

  • Page 8

    Drive Signals Timing Diagrams CLOCK UPPER1 UPPER2 SYNC1 SYNC2 LOWER1 I LOWER1 LOWER2 I LOWER2 RAMP ADJUST OUTPUT TO PWM LOGIC T1 NOTES Leading edge blanking Resonant delay dead time ...

  • Page 9

    Shutdown Timing Diagrams LATSD ON/OFF A VDD PKILIM > BGREF ILIM_OUT PKILIM < BGREF SOFT START DRIVER ENABLE SOFT-START SHUTDOWN FAULT OFF Shutdown Timing Descriptions A (ON/OFF) - When the ON/OFF is pulled low, the soft-start capacitor is discharged and ...

  • Page 10

    Block/Pin Functional Descriptions Detailed descriptions of each individual block in the functional block diagram on page 3 are included in this section. Application information and design considerations for each pin and/or each block are also included. • IC Bias Power ...

  • Page 11

    CT (pF) RECOMMENDED RANGE FIGURE FREQUENCY - Note that the capacitance of a scope probe (~12pF for single ended) would induce a smaller frequency ...

  • Page 12

    ... The UVLO holds all the drivers low until the VDD has reached the turn-on threshold VDD - The upper drivers require assistance of external level- shifting circuits such as Intersil’s HIP2100 or pulse transformers to drive the upper power switches of a bridge converter. • Peak Current Limit (PKILIM) ...

  • Page 13

    R_RESDLY (kΩ) FIGURE 7. R_RESDLY vs RESDLY • Leading Edge Blanking (R_LEB current mode control, the sensed switch (FET) current is processed ...

  • Page 14

    Ramp Adjust (R_RA, ISENSE) - The ramp adjust block adds an offset component (200mV) and a slope adjust component to the ISENSE signal before processing it at the PWM Logic block, as shown in Figure 9. This ensures that ...

  • Page 15

    Power Good (DCOK) - DCOK pin is an open drain output capable of sinking 5mA low when the output voltage is within the UVOV window. The static regulation limit is ± the 5% is the dynamic regulation ...

  • Page 16

    Additional Applications Information Table 1 highlights parameter setting for the ISL6551. Designers can use this table as a design checklist. For TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST VDD = 12V at room temperature, unless otherwise stated. PARAMETER PIN NAME Frequency Dead ...

  • Page 17

    Figure 13 shows the block diagram of a power supply system employing the ISL6551 full bridge controller. The ISL6551 not only is a full bridge PWM controller but also can be used as a push-pull PWM controller. Users can design ...

  • Page 18

    Current Sense T_CURRENT Q3_S Q4_S FIGURE 14A. TWO-LEG SENSE CURRENT_SEN_P FIGURE 14B. TOP SENSE Q3_S & Q4_S RSENSE FIGURE 14C. RESISTOR SENSE (PRIMARY CONTROL) Two-Leg Sense - Senses the current that flows through both lower primary FETs. ...

  • Page 19

    Feedback EAI VOPOUT FIGURE 16A. SECONDARY CONTROL VREF = 5V VOPOUT IL207 TL431 FIGURE 16B. PRIMARY CONTROL Secondary Control - In secondary side control systems, only a few resistors and capacitors are required to complete the feedback loop. Primary Control ...

  • Page 20

    ... The secondary winding carries all the load, i.e., all the load is reflected to the primary. 20 ISL6551 Supervisor Circuits (1) INTEGRATED SOLUTION • Intersil ISL6550 Supervisor And Monitor (SAM). Its QFN package requires less space than the SOIC package. VOPOUT VREF5 F OUT BDAC • ...

  • Page 21

    Output Filter L S+ OUT S– FIGURE 20A. CURRENT DOUBLER FILTER L OUT V F OUT F CLOCK FIGURE 20B. CONVENTIONAL FILTER Current Doubler Filter - Two inductors are needed, but they can be integrated and coupled into one core. ...

  • Page 22

    Primary FET Drivers (1) PUSH-PULL DRIVERS LOWER1 LOWER2 FIGURE 23A. PUSH-PULL MEDIUM CURRENT DRIVERS Push-Pull Medium Current Drivers - Upper drivers are not used. No external drivers are required. Secondary control. Operate at the switching frequency. Push-Pull High Current Drivers ...

  • Page 23

    ... Full Bridge Primary Control - Lower drivers can directly drive the power switches, while upper drivers require the assistance of level-shifting circuits such as a pulse transformer or Intersil’s HIP2100 half-bridge driver. External high current drivers are not required in medium power applications, but level-shifting circuits are still required for upper drivers ...

  • Page 24

    Simplified Typical Application Schematics SB+12V UPPER1 UPPER2 LOWER1 LOWER2 SA+12V + OUT - PGND UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2 LED SHARE BUS 200W TELECOMMUNICATION POWER SUPPLY (SEE AN1002 FOR DETAILS) SB+48V VDD LO HB VSS ...

  • Page 25

    Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...

  • Page 26

    ... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...