ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 12

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

• Drivers (Upper1, Upper2, Lower1, Lower2)
• Peak Current Limit (PKILIM)
- Per Equation 3, the clamping voltage is a function of the
- The soft-start rise time (T
- The two upper drivers are driven at a fixed 50% duty
- Each driver is capable of driving capacitive loads up to CL
- The UVLO holds all the drivers low until the VDD has
- The upper drivers require assistance of external level-
- When the voltage at PKILIM exceeds the BGREF voltage,
- The peak current shutdown threshold is usually set slightly
charge current Iss. For a more predictable clamping
voltage, the CSS pin can be connected to a reference-
based clamp circuit as shown in Figure 5. To make the
Vclamp less dependent on the soft-start current (Iss),
the currents flowing through R1 and R2 should be
scaled much greater than Iss. The relationship of this
circuit can be found in Equation 4.
Equation 5. The rise time (T
approximated with Equation 6.
T ss
T
cycle and the two lower drivers are PWM-controlled on
the trailing edge while the leading edge employs resonant
delay. They are biased by VDDP1 and VDDP2,
respectively.
at 1MHz clock frequency and higher loads at lower
frequencies on a layout with high effective thermal
conductivity.
reached the turn-on threshold VDD
shifting circuits such as Intersil’s HIP2100 or pulse
transformers to drive the upper power switches of a bridge
converter.
the gate pulses are terminated and held low until the next
clock cycle. The peak current limit circuit has a high-speed
loop with propagation delay IpkDel. Peak current
shutdown initiates a soft-start sequence.
higher than the normal cycle-by-cycle PWM peak current
limit (Vclamp) and therefore will normally only be activated
Vclamp
V
rise
REF
FIGURE 5. REFERENCE-BASED CLAMP CIRCUIT
=
R2
=
R1
Vclamp Css
---------------------------------------
EANI Css
--------------------------------
≈
Iss
Iss
Iss
•
×
R1
--------------------- -
R1
×
×
+
R2
R2
+
12
Vref
ss
CSS
) can be calculated with
rise
•
(s)
(s)
----------------------
R1
) of the output voltage is
R2
ON
+
R2
.
(EQ. 5)
(EQ. 6)
(EQ. 4)
ISL6551
• Latching Shutdown (LATSD)
• ON/OFF (ON/OFF)
• Resonant Delay (R_RESDLY)
- In general, the trip point is a little smaller than the BGREF
- A high TTL level on LATSD latches the IC off. The IC goes
- This pin can be used to latch the power supply off on
- A high standard TTL input (safe also for VDD level) signals
- This pin is a non-latching input and can accept an enable
- A resistor tied between R_RESDLY and VSS determines
- Figure 7 illustrates the relationship of the value of the
t
in a short-circuit condition. The limit can be set with a
resistor divider from the ISENSE pin. The resistor divider
relationship is defined in Equation 7.
due to the noise and/or ripple at the BGREF.
--------------------------------------
Rdown
into a low power mode and is reset only after the power at
the VDD pin is removed completely. The ON/OFF cannot
reset the latch.
output overvoltage or other undesired conditions.
the controller to turn on. A low TTL input turns off the
controller and terminates all drive signals including the
SYNC outputs. The soft-start is reset.
command when monitoring the input voltage and the
thermal condition of a converter.
the delay that is required to turn on a lower FET after its
corresponding upper FET is turned off. This is the resonant
delay, which can be estimated with Equation 8.
resistor (R_RESDLY) and the resonant delay (t
The percentages in the figure are the tolerances at the two
end points of the curve.
RESDLY
FIGURE 6. PEAK CURRENT LIMIT SET CIRCUIT
Rdown
R
+
= 4.01 x R_RESDLY/k
DOWN
Rup
R
UP
=
-----------------------------------------
ISENSE max
BGREF
(
Ω
)
+ 13 (ns)
ISENSE
PKILIM
January 3, 2006
RESDLY
(EQ. 8)
(EQ. 7)
FN9066.5
).