ISL6522EVAL1 Intersil, ISL6522EVAL1 Datasheet - Page 11

• Manufacturer Part Number: ISL6522EVAL1
• Description: EVALUATION BOARD ISL6522
• Manufacturer: Intersil

Specifications of ISL6522EVAL1

• Main Purpose: DC/DC, Step Down
• Voltage - Input: 10.8 ~ 13.2V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6522
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Voltage - Output: -
• Power - Output: -
• Frequency - Switching: -
• Outputs And Type: -

switch realizes most of the switching losses when the converter
is sinking current (see the equations below).
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated by the ISL6522 and do not
heat the MOSFETs. However, large gate-charge increases
the switching interval, t
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for
use with the ISL6522. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
less the boot diode drop (V
turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to PVCC.
Losses while Sinking Current
Losses while Sourcing Current
P
P
P
P
UPPER
LOWER
LOWER
UPPER
Where: D is the duty cycle = V
= Io
= Io
=
=
t
F
SW
Io
S
Io
2
2
2
is the switching frequency.
x r
2
x r
is the switching interval, and
×
×
DS(ON)
r
DS(ON)
r
DS ON
DS ON
(
(
SW
x D
x (1 - D)
)
CC
)
×
×
which increases the upper
D
D
(
. The boot capacitor, C
) when the lower MOSFET, Q2
11
1 D
+
–
1
-- - Io
2
OUT
⋅
)
+
/ V
×
1
-- - Io
2
V
⋅
IN
IN
,
×
×
CC
V
t
SW
IN
. For Q2, a
×
×
t
F
SW
S
BOOT
×
F
S
CC
ISL6522
Figure 10 shows the upper gate drive supplied by a direct
connection to V
converter systems where the main input voltage is +5V
less. The peak upper gate-to-source voltage is approximately
V
for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage rating
exceeds the maximum voltage applied to PV
FIGURE 10. UPPER GATE DRIVE - DIRECT V
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
CC
ISL6522
ISL6522
+
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
+
-
-
less the input supply. For +5V main power and +12V
+12V
+12V
VCC
VCC
CC
+
GND
D
GND
. This option should only be used in
V
BOOT
D
BOOT
UGATE
PHASE
LGATE
PGND
PVCC
BOOT
UGATE
PHASE
LGATE
PGND
PVCC
-
+5V
+5V
OR +12V
OR +12V
C
BOOT
Q1
Q2
Q1
+5V OR +12V
Q2
+5V OR LESS
D2
CC
CC
D2
NOTE:
V
V
NOTE:
NOTE:
V
NOTE:
V
G-S
G-S
.
DRIVE OPTION
G-S
G-S
≈
≈
≈
March 10, 2006
≈
V
V
PVCC
PVCC
CC
CC
DC
FN9030.8
- V
- 5V
DC
or
D