ISL6530EVAL1 Intersil, ISL6530EVAL1 Datasheet - Page 11

• Manufacturer Part Number: ISL6530EVAL1
• Description: EVALUATION BOARD 1 ISL6530
• Manufacturer: Intersil

Specifications of ISL6530EVAL1

• Main Purpose: Special Purpose DC/DC, DDR Memory Supply
• Outputs And Type: 2, Non-Isolated
• Power - Output: 31.25W
• Voltage - Output: 2.5V, 1.25V
• Current - Output: 10A, 5A
• Voltage - Input: 4.5 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6530
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES
KEY
ISL6530
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
UGATE1
UGATE2
PHASE1
LGATE1
SENSE1
PHASE2
LGATE2
SENSE2
AND ISLANDS
COMP1
COMP1
BOOT1
PGND1
BOOT2
PGND2
GND
VCC
FB1
FB1
C
+5V V
BP
R
R
C
C
C
2A
C
PHASE2
2B
2A
IN
2B
PHASE1
D2
BOOT2
BOOT1
R4
+5V V
11
D1
C
C
V
1A
1B
IN
DDQ
C
C
R
R
3A
3B
Q1
Q3
Q2
Q4
1A
1B
R
R
3A
3B
L
L
C
OUT1
OUT2
IN
C
C
OUT1
OUT2
V
V
DDQ
TT
ISL6530
The switching components should be placed close to the
ISL6530 first. Minimize the length of the connections
between the input capacitors, C
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper MOSFET and lower diode and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitor, C
VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.
Feedback Compensation
Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
error amplifier (Error Amp) output (V
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V
the PHASE node. The PWM wave is smoothed by the output
filter (L
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ∆V
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6530) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
F
1. Pick gain (R
2. Place first zero below filter’s double pole (~75% F
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
3
LC
OUT
, C
=
FB
1
) is regulated to the Reference voltage level. The
----------------------------------------- -
2π x
O
, C
. The goal of the compensation network is to provide
and C
2
, and C
0dB
OUT
L
1
O
O
) and adequate phase margin. Phase margin
x C
2
).
/V
/R
3
E/A
O
1
) in Figure 7. Use these guidelines for
LC
) for desired converter bandwidth.
. This function is dominated by a DC
and a zero at F
O
F
and C
ESR
IN
, and the power switches
OSC
=
O
------------------------------------------ -
2π x ESR x C
E/A
), with a double pole
ESR
) is compared with
IN
. The DC Gain of
1
) divided by the
BP
November 15, 2004
, close to the
O
LC
0dB
).
FN9052.2
1
IN
, R
and
IN
at
2
,