ISL6530EVAL2 Intersil, ISL6530EVAL2 Datasheet - Page 8

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ISL6530EVAL2

Manufacturer Part Number
ISL6530EVAL2
Description
EVALUATION BOARD 2 ISL6530
Manufacturer
Intersil
Datasheet

Specifications of ISL6530EVAL2

Main Purpose
Special Purpose DC/DC, DDR Memory Supply
Outputs And Type
2, Non-Isolated
Power - Output
31.25W
Voltage - Output
2.5V, 1.25V
Current - Output
10A, 5A
Voltage - Input
4.5 ~ 5.5V
Regulator Topology
Buck
Frequency - Switching
300kHz
Board Type
Fully Populated
Utilized Ic / Part
ISL6530
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Shoot-Through Protection
A shoot-through condition occurs when both the upper
MOSFET and lower MOSFET are turned on simultaneously,
effectively shorting the input voltage to ground. To protect
the regulators from a shoot-through condition, the ISL6530
incorporates specialized circuitry which insures that
complementary MOSFETs are not ON simultaneously.
The adaptive shoot-through protection utilized by the V
regulator looks at the lower gate drive pin, LGATE1, and the
phase node, PHASE1, to determine whether a MOSFET is
ON or OFF. If PHASE1 is below 0.8V, the upper gate is
defined as being OFF. Similarly, if LGATE1 is below 0.8V, the
lower MOSFET is defined as being OFF. This method of
shoot-through protection allows the V
source current only.
Due to the necessity of sinking current, the V
employs a modified protection scheme from that of the
V
LGATE2 to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the other MOSFET is
turned ON.
Since the voltage of the lower MOSFET gates and the upper
MOSFET gate of the V
determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing
such measures. Doing so may interfere with the shoot-
through protection.
Power Down Mode
DDRAM systems include a sleep state in which the V
voltage to the memories is maintained, but signaling is
suspended. During this mode the V
no longer needed. The only load placed on the V
the leakage of the associated signal pins of the DDRAM and
memory controller ICs.
DDQ
0V
regulator. If the voltage from UGATE2 or from
(1V/DIV)
FIGURE 2. SOFT-START INTERVAL
T0
T1
TT
supply are being measured to
TIME
8
T2
TT
DDQ
termination voltage is
V
V
VCC (5V)
DDQ
TT
(1.25V)
regulator to
(2.5V)
TT
regulator
TT
bus is
DDQ
DDQ
ISL6530
When the V2_SD input of the ISL6530 is driven high, the
V
state the main V
upper and lower MOSFETs being turned off. The V
is maintained at close to .5xVdd via a low current window
regulator which drives V
Maintaining V
and enables rapid wake-up from sleep mode without the
need of softstarting the V
down mode, PGOOD is held LOW.
Output Voltage Selection
The output voltage of the V
programmed to any level between V
internal reference, 0.8V. An external resistor divider is used
to scale the output voltage relative to the reference voltage
and feed it back to the inverting input of the error amplifier,
see Figure 3. However, since the value of R1 affects the
values of the rest of the compensation components, it is
advisable to keep its value less than 5kΩ. R4 can be
calculated based on the following equation:
If the output voltage desired is 0.8V, simply route VOUT1
back to the FB pin through R1, but do not populate R4.
V
The ISL6530 allows the designer to bypass the internal 50%
tracking of V
ISL6530 was designed to divide down the V
50% through two internal matched resistances. These
resistances are typically 200kΩ.
R4
TT
TT
=
regulator is placed into a “sleep” state. In the sleep
FIGURE 3. OUTPUT VOLTAGE SELECTION OF V
Reference Overdrive
------------------------------------- -
V
OUT1
+5V
R1 0.8V
ISL6530
VCC
×
DDQ
TT
0.8V
TT
at .5xV
that is used as the reference for V
LGATE1
BOOT1
UGATE1
PHASE1
FB1
COMP1
regulator is disabled, with both the
D1
DDQ
TT
TT
C2
DDQ
via the SENSE2 pin.
C4
regulator. During this power
C1
consumes negligible power
R2
regulator can be
Q2
Q1
IN
L
C
OUT
R4
OUT1
(i.e. +5V) and the
R1
C3
+
DDQ
November 15, 2004
R3
voltage by
V
DDQ
TT
TT
DDQ
FN9052.2
. The
bus

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