ISL6530EVAL2

Manufacturer Part NumberISL6530EVAL2
DescriptionEVALUATION BOARD 2 ISL6530
ManufacturerIntersil
ISL6530EVAL2 datasheet
 


Specifications of ISL6530EVAL2

Main PurposeSpecial Purpose DC/DC, DDR Memory SupplyOutputs And Type2, Non-Isolated
Power - Output31.25WVoltage - Output2.5V, 1.25V
Current - Output10A, 5AVoltage - Input4.5 ~ 5.5V
Regulator TopologyBuckFrequency - Switching300kHz
Board TypeFully PopulatedUtilized Ic / PartISL6530
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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While the V
supply “floats”, it is held to about 50% of
TT
V
via a low current window regulator which drives V
DDQ
via the SENSE2 pin. The window regulator can overcome up
to at least ±10mA of leakage on V
.
TT
While V2_SD is high, PGOOD is low.
PHASE1 and PHASE2
Connect PHASE1 and PHASE2 to the corresponding upper
MOSFET source. This pin is used as part of the upper
MOSFET bootstrapped drives. PHASE1 is used to monitor
the voltage drop across the upper MOSFET of the V
regulator for over-current protection. The PHASE1 pin is
monitored by the adaptive shoot through protection circuitry
to determine when the upper FET of the V
turned off.
FB1, COMP1, FB2, and COMP2
COMP1, COMP2, FB1, and FB2 are the available external
pins of the error amplifiers. The FB1 and FB2 pins are the
inverting inputs of each error amplifier and the COMP1 and
COMP2 pins are the associated outputs. An appropriate AC
network across these pins is used to compensate the
voltage-controlled feedback loop of each converter.
VREF and VREF_IN
VREF produces a voltage equal to one half of the voltage on
SENSE1. This low current output is connected to the VREF
input of the DDRAM devices being powered. This same
voltage is used as the reference input of the V
amplifier. Thus V
is controlled to 50% of V
TT
VREF_IN is used as an option to overdrive the internal
resistor divider network that sets the voltage for both
VREF_OUT and the reference voltage for the V
100pF capacitor between VREF_IN and ground is
recommended for proper operation.
PVCC1
This is the positive supply for the lower gate driver, LGATE1.
PVCC1 is connected to a well decoupled 5V.
SENSE1 and SENSE2
Both SENSE1 and SENSE2 are connected directly to the
regulated outputs of the V
and V
DDQ
TT
respectively. SENSE1 is used as an input to create the
voltage at VREF_OUT and the reference voltage for the V
supply. SENSE2 is used as the regulation point for the
window regulator that is enabled in V2_SD mode.
Functional Description
Overview
The ISL6530 contains control and drive circuitry for two
synchronous buck PWM voltage regulators. Both regulators
utilize 5V bootstrapped output topology to allow use of low
cost N-channel MOSFETs. The regulators are driven by
7
ISL6530
300kHz clocks. The clocks are phase locked and displaced
o
90
to minimize noise coupling between the controllers.
TT
The first regulator includes a precision 0.8V reference and is
intended to provide the proper V
system. The V
protection utilizing the r
Following a fault condition, the V
via a digital softstart circuit.
Included in the ISL6530 is a precision V
output. V
DDQ
is derived via a precision internal resistor divider connected
to the SENSE1 terminal.
supply has
DDQ
The second PWM regulator is designed to provide V
termination for the DDRAM signal lines. The reference to the
V
regulator is V
TT
termination voltage equal to .5xV
MOSFET of the V
V
voltage. The V
DDQ
sinking and sourcing current on the V
Two benefits result from the ISL6530 dual controller
topology. First, as VREF is always .5xV
will track the V
the overcurrent protection incorporated into the V
will simultaneously protect the V
Initialization
error
The ISL6530 automatically initializes upon application of
TT
.
input power. Special sequencing of the input supplies is not
DDQ
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltage at the VCC pin. The
POR function initiates soft-start operation after the 5V bias
supply. A
TT
supply voltage exceeds its POR threshold.
Soft-Start
The POR function initiates the digital soft start sequence. The
PWM error amplifier reference input for the VDDQ regulator is
clamped to a level proportional to the soft-start voltage. As the
soft-start voltage slews up, the PWM comparator generates
PHASE pulses of increasing width that charge the output
capacitor(s). This method provides a rapid and controlled
output voltage rise. The soft start sequence typically takes
supplies,
about 7ms.
TT
With the V
automatically track the ramp of the V
enabling a soft-start for V
Figure 2 shows the soft-start sequence for a typical application.
At t0, the +5V VCC bias voltage starts to ramp. Once the
voltage on VCC crosses the POR threshold at time t1, both
outputs begin their soft-start sequence. The triangle waveforms
from the PWM oscillators are compared to the rising error
amplifier output voltage. As the error amplifier voltage
increases, the pulse-widths on the UGATE pins increase to
reach their steady-state duty cycle at time t2.
to a DDRAM memory
DDQ
controller implements overcurrent
DDQ
of the upper MOSFET.
DS(ON)
regulator is softstarted
DDQ
reference
REF
is a buffered representation of .5xV
REF
. Thus the V
regulator provides a
REF
TT
. The drain of the upper
DDQ
supply is connected to the regulated
TT
controller is designed to enable both
TT
rail.
TT
, the V
DDQ
supply during softstart cycles. Second,
DDQ
supply.
TT
1
regulator reference held at
-- - V
TT
DDQ
2
softstart, thus
DDQ
.
TT
. V
DDQ
REF
TT
supply
TT
supply
DDQ
it will
FN9052.2
November 15, 2004