ISL6521EVAL1Z Intersil, ISL6521EVAL1Z Datasheet - Page 8

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ISL6521EVAL1Z

Manufacturer Part Number
ISL6521EVAL1Z
Description
EVALUATION BOARD 1 ISL6521
Manufacturer
Intersil
Datasheets

Specifications of ISL6521EVAL1Z

Main Purpose
DC/DC, Step Down with LDO
Outputs And Type
4, Non-Isolated
Voltage - Output
1.5V, 2.5V, 3.3V, 1.8V
Current - Output
5A, 1A, 1A, 120mA
Voltage - Input
4.5 ~ 5.5V
Regulator Topology
Buck
Frequency - Switching
300kHz
Board Type
Fully Populated
Utilized Ic / Part
ISL6521
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
and Z
a closed loop transfer function with high 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1 , R2 ,
R3 , C1 , C2 , and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
F
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Z1
Z2
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
V
OSC
=
=
FB
-----------------------------------
--------------------------------------------------------- -
. The goal of the compensation network is to provide
OSC
×
×
V
ST
ND
ST
ND
0dB
R
(
E/A
R
1
COMPENSATION DESIGN
2 C1
S1
Zero Below Filter’s Double Pole (~75% F
DETAILED COMPENSATION COMPONENTS
Pole at the ESR Zero
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
ISL6521
×
ERROR
) and adequate phase margin. Phase margin
AMP
1
+
COMP
PWM
R3
Z
+
COMP
FB
-
+
)
C1
×
0.8V
C3
C2
DRIVER1
+
R2
-
DRIVER
SYNC
Z
0.8V
8
F
F
IN
P1
P2
FB
=
=
Z
V
------------------------------------------------------ -
-----------------------------------
FB
IN
PHASE
×
×
C3
(PARASITIC)
R
R
R
1
R
Z
2
3
L
S1
P1
IN
O
×
×
1
R3
C3
ESR
C1
--------------------- -
C1
C
V
O
OUT
×
+
+
0dB
C2
C2
V
OUT
LC
and
)
ISL6521
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 5. Using the above
guidelines should yield a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 6 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Individual Output Disable
The PWM and linear controllers can independently be
shutdown.
To disable the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached R
possibility of OC trips at levels different than predicted, a
C
larger than the output capacitance of the pull-down device,
has to be used in parallel with R
Upon turn-off of the pull-down device, the switching regulator
undergoes a soft-start cycle.
To disable a particular linear controller, pull and hold the
respective FB pin above a typical threshold of 1.25V. One
way to achieve this task is by using a logic gate coupled
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
OCSET
100
-20
-40
-60
80
60
40
20
0
and Z
10
20
MODULATOR
capacitor with a value of an order of magnitude
log
IN
GAIN
to provide a stable, high bandwidth (BW) overall
------------ -
R
100
R2
OCSET
F
S1
Z1
F
1K
LC
pull-up) below 1.25V. To minimize the
F
FREQUENCY (Hz)
Z2
F
ESR
10K
F
OCSET
P1
100K
F
P2
(1nF recommended).
1M
ERROR AMP GAIN
COMPENSATION
OPEN LOOP
CLOSED LOOP
20
10M
log
GAIN
GAIN
----------- -
V
V
PP
IN
P2

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