ISL6548A-6506EVAL1Z

Manufacturer Part NumberISL6548A-6506EVAL1Z
DescriptionEVALUATION BOARD ISL6548A-6506
ManufacturerIntersil
ISL6548A-6506EVAL1Z datasheets
 


Specifications of ISL6548A-6506EVAL1Z

Main PurposeSpecial Purpose DC/DC, DDR Memory SupplyOutputs And Type7, Non-Isolated
Power - Output178WVoltage - Output1.8V, 3.3V, 5V, 1.5V, 1.2V, 2.5V, 0.9V
Current - Output15A, 14A, 14A, 10A, 5A, 5A, 2AVoltage - Input3.3V, 5V, 12V
Regulator TopologyBuckBoard TypeFully Populated
Utilized Ic / PartISL6506, ISL6548ALead Free Status / RoHS StatusLead free / RoHS Compliant
Frequency - Switching-  
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Data Sheet
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6548A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply V
during S0/S1 and S3 states. During S0/S1
DDQ
state, a fully integrated sink-source regulator generates an
accurate (V
/2) high current V
voltage without the
DDQ
TT
need for a negative supply. A second PWM controller, which
requires external MOSFET drivers, is available for regulation
of the GMCH Core voltage. A sink/source LDO controller is
also integrated for the CPU/GMCH V
TT
regulation. Another LDO is available for the ICH7 voltage.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±
2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU V
TT
is within spec and operational.
All outputs, except V
, have undervoltage protection. The
ICH7
switching regulator also has overvoltage and overcurrent
protection. Thermal shutdown is integrated.
1
January 3, 2006
Features
• Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V
- 3A Integrated Sink/Source Linear Regulator with
Accurate V
- PWM Regulator for GMCH Core
- Sink/Source LDO Regulator for CPU/GMCH V
Termination
- LDO Regulator for ICH7
• ACPI Compliant Sleep State Control
termination voltage
• Glitch-free Transitions During State Changes
• V
PWM Controller Drives Low Cost N-Channel
DDQ
MOSFETs
• 250kHz Constant Frequency Operation
- Both PWM Controllers are Phase Shifted 180°
• Tight Output Voltage Regulation
- All Outputs:
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
termination voltage
• Under and Overvoltage Monitoring
• OCP on the V
• Integrated Thermal Shutdown Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI Compliant PCs
• Graphics Cards - GPU and Memory Supplies
• ASIC Power Supplies
• Embedded Processor and I/O Supplies
• DSP Supplies
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
All other trademarks mentioned are the property of their respective owners.
ISL6548A
FN9189.2
/2 Divider Reference for DDR V
DDQ
±
2% Over Temperature
Switching Regulator
DDQ
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved
DDQ
TT
TT

ISL6548A-6506EVAL1Z Summary of contents

  • Page 1

    ... Data Sheet ACPI Regulator/Controller for Dual Channel DDR Memory Systems The ISL6548A provides a complete ACPI compliant power solution for DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply V during S0/S1 and S3 states. During S0/S1 DDQ state, a fully integrated sink-source regulator generates an ...

  • Page 2

    ... MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 ISL6548A Pinout PKG. PACKAGE DWG 6x6 QFN L28.6x6 (Pb-free 6x6 QFN L28.6x6 5VSBY (Pb-free) Tape and Reel S3# P12V GND DDR_VTT DDR_VTT VDDQ ISL6548A (QFN) TOP VIEW GND ...

  • Page 3

    Block Diagram 180° PHASE PWM4 SHIFT COMP4 EA4 FB4 P12V EA2 DRIVE2_U FB2 DRIVE2_L P12V EA3 DRIVE3 FB3 S3# S5# 5VSBY P12V FB EA1 POR EA1 ACTIVE IN S3 MONITOR AND CONTROL SOFT-START & ENABLE A SOFT-START & ENABLE B ...

  • Page 4

    ... ISL6548A 12V 5VSBY ISL6548A SLEEP STATE LOGIC PWM CONTROLLER PWM CONTROLLER VTT REGULATOR LINEAR CONTROLLER LINEAR CONTROLLER 5VSBY 12V VIDPGD S5# OCSET S3# ISL6548A UGATE PHASE PWM4 LGATE C5 COMP4 DDR_VDDQ(x2 FB4 R8 VREF_IN DRIVE2_U FB2 DDR_VTT(x2) R10 DDR_VTTSNS DRIVE2_L DRIVE3 5VDUAL 3V3ATX or V GMCH ...

  • Page 5

    ... DC Gain Gain-Bandwidth Product Slew Rate CONTROL I/O (S3#, S5#) LOW Level Input Threshold HIGH Level Input Threshold 5 ISL6548A Thermal Information Thermal Resistance (Typical, Notes 1, 2) QFN Package . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature (Plastic Package 150° +6.0V Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s 300° ...

  • Page 6

    ... TT_GMCH/CPU Thermal Shutdown Limit Functional Pin Description 5VSBY (Pin 1) 5VSBY is the bias supply of the ISL6548A typically connected to the 5V standby rail of an ATX power supply. During S4/S5 sleep states the ISL6548A enters a reduced power mode and draws less than 1mA (I 5VSBY supply. The supply to 5VSBY should be locally bypassed using a 0.1µ ...

  • Page 7

    ... During S0/S1 states, the VDDQ DDQ pins serve as inputs to the V regulator and to the V TT Reference precision divider. 7 ISL6548A DDR_VTT (Pins 5, 6) The DDR_VTT pins should be connect externally together. During S0/S1 states, the DDR_VTT pins serve as the outputs of the V TT regulator is disabled. ...

  • Page 8

    ... ISL6548A receives its bias voltage from the 5V Standby bus (5VSBY). Once the 5VSBY rail has exceeded the POR threshold, the ISL6548A will remain in an internal S5 state until both the SLP_S3 and SLP_S5 signal have transitioned high and the 12V POR threshold has been exceeded by the ...

  • Page 9

    ... SLP_S3# SLP_S5# 12V POR 12V 0V V DDQ_DDR 0V V GMCH 0V V TT_GMCH/CPU 0V V ICH7 0V V DDQ_DDR V TT_DDR 0V VIDPGD (3 SOFT-START CYCLES Soft-Start Rise Time Dependent Upon Capacitor On V TT_DDR V FLOATING TT_DDR (3 SOFT-START CYCLES FIGURE 1. ISL6548A TIMING DIAGRAM Pin REF_IN ...

  • Page 10

    ... The ISL6548A will immediately shut down when the Fault Counter reaches a count of 4 when the system is restarting from an S5 state into the active, or S0, state. The ISL6548A will immediately shut down when the Fault Counter reaches a count any other time. ...

  • Page 11

    ... There are two sets of critical components in the ISL6548A OCSET switching converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise ...

  • Page 12

    ... ISL6548A the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. The switching components should be placed close to the ISL6548A first. Minimize the length of the connections between the input capacitors placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible ...

  • Page 13

    ... If the output voltage desired is 0.8V, simply route the output voltage back to the respective FB pin through the feedback resistor and do not populate the output voltage programming resistor. The output voltage for the internal V is set internal to the ISL6548A to track the V 50%. There is no need for external programming resistors ...

  • Page 14

    ... Given a sufficiently fast control loop design, the ISL6548A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...

  • Page 15

    ... MOSFET’s body diode. The gate-charge losses are dissipated in part by the ISL6548A and do not significantly heat the MOSFETs. However, large gate-charge increases the switching interval, t which increases the MOSFET switching losses. Ensure ...

  • Page 16

    ... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 ISL6548A L28.6x6 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJC ISSUE C) ...