ISL6527EVAL1 Intersil, ISL6527EVAL1 Datasheet - Page 10

• Manufacturer Part Number: ISL6527EVAL1
• Description: EVALUATION BOARD SOIC ISL6527
• Manufacturer: Intersil

Specifications of ISL6527EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 0.75 ~ 3V
• Current - Output: 5A
• Voltage - Input: 3.3 ~ 5V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6527
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ΔV
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6527, ISL6527A) and the impedance
networks Z
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f
margin. Phase margin is the difference between the closed
loop phase at f
the compensation network’s poles, zeros and gain to the
components (R
F
F
LC
ESR
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
=
ISL6527, ISL6527A
=
----------------------------------------- -
2π x
------------------------------------------ -
2π x ESR x C
IN
CPVOUT
L
UGATE
PHASE
OUT
1
LGATE
KEY
COMP
BOOT
AND ISLANDS
O
and Z
1
GND
VCC
0dB
1
x C
FB
, R
VIA CONNECTION TO GROUND PLANE
/V
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
E/A
O
and 180°. Equations 7 through 10 relate
FB
2
CBP
CVCC
LC
, R
O
. The goal of the compensation
. This function is dominated by a DC
3
and a zero at F
R2
C2
, C
CBOOT
PHASE
R4
+3.3V VIN
O
1
10
, C
and C
D1
C1
2
C3
, and C
0dB
OSC
Q1
Q2
R1
O
R3
), with a double pole
) and adequate phase
ESR
.
CIN
LOUT
3
COUT
) in Figure 5. Use
IN
. The DC Gain of
) divided by the
VOUT
ISL6527, ISL6527A
(EQ. 5)
(EQ. 6)
these guidelines for locating the poles and zeros of the
compensation network:
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
F
F
F
F
1. Pick gain (R
2. Place first zero below filter’s double pole (~75% F
3. Place second zero at filter’s double-pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
Z1
P1
Z2
P2
DVOSC
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
=
=
=
=
--------------------------------- -
2π
------------------------------------------------------ -
2π x R
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
×
OSC
R
(
1
1
2
2
3
COMPENSATION DESIGN
COMPARATOR
1
×
x
x C
ERROR
AMP
+
DETAILED COMPENSATION COMPONENTS
1
VE/A
C
1
2
ISL6527
⎛
⎜
⎝
R
/R
2
C
--------------------- -
PWM
C
3
3
1
1
1
) x C
ZFB
+
-
) for desired converter bandwidth.
x C
+
-
+
COMP
C
C2
REFERENCE
2
2
REFERENCE
3
⎞
⎟
⎠
C1
+
-
DRIVER
DRIVER
R2
ZIN
FB
ZFB
PHASE
(PARASITIC)
VIN
C3
LO
ZIN
R1
November 18, 2008
R3
ESR
CO
VOUT
LC
(EQ. 10)
FN9056.10
(EQ. 7)
(EQ. 8)
(EQ. 9)
).
VOUT