ISL6523EVAL1 Intersil, ISL6523EVAL1 Datasheet - Page 8

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ISL6523EVAL1

Manufacturer Part Number
ISL6523EVAL1
Description
EVALUATION BOARD VRM8.5 ISL6523
Manufacturer
Intersil
Datasheet

Specifications of ISL6523EVAL1

Main Purpose
Special Purpose DC/DC, VRM Supply
Outputs And Type
4, Non-Isolated
Voltage - Output
1.05 ~ 1.825V, 1.2V, 1.5V, 1.8V
Current - Output
14A, 4A, 1A, 1A
Voltage - Input
3.3V, 5V, 12V
Regulator Topology
Buck
Frequency - Switching
200kHz
Board Type
Fully Populated
Utilized Ic / Part
ISL6523
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
overcurrent latch and generates a soft-started ramp-up of
the outputs 1, 2, and 3.
OUT1 Overvoltage Protection
The overvoltage circuit provides protection during the initial
application of power. For voltages on the VCC pin below the
power-on reset (and above ~4V), the output level is
monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2, is driven on.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
Both PWM controllers use the upper MOSFET’s on-
resistance, r
against shorted outputs. Both linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive currents.
Figure 7 illustrates the overcurrent protection with an overload
on OUT2. The overload is applied at T0 and the current
increases through the inductor (L
comparator trips when the voltage across Q3 (i
exceeds the level programmed by R
outputs 1, 2, and 3, discharges soft-start capacitor C
28µA current sink, and increments the counter. Soft-start
capacitor C
and initiates a soft-start cycle with the error amplifiers
clamped by soft-start. With OUT2 still overloaded, the inductor
current increases to trip the overcurrent comparator. Again,
this inhibits the outputs, but the soft-start voltage continues
increasing to above 4.0V before discharging. The counter
increments to 2. The soft-start cycle repeats at T3 and trips
the overcurrent comparator. The SS pin voltage increases to
OC1
SS24
UV3
SS13
UV4
OC2
OV
0.8V
4V
4V
FIGURE 6. FAULT LOGIC - SIMPLIFIED SCHEMATIC
SS13UP
SS13
DS(ON)
SS24UP
is quickly discharged. C
to monitor the current for protection
LATCH
S
R
OC
Q
LATCH
R
S
OC
Q
POR
8
R
COUNTER
OUT2
OCSET
COUNTER
). At time T1, the OC2
SS24
. This inhibits
recharges at T2
R
D
LATCH
INHIBIT1,2,3
FAULT
S
R
r
DS(ON)
SS24
Q
Q
SSDOWN
FAULT
with
)
ISL6523
above 4.0V at T4 and the counter increments to 3. This sets
the fault latch to disable the converter.
The PWM1 controller operates in the same way as PWM2 to
overcurrent faults. Additionally, the two linear controllers
monitor the VSEN pins for under-voltage. Should excessive
currents cause VSEN3 or VSEN4 to fall below the linear
under-voltage threshold, the respective UV signals set the
OC latch or the FAULT latch, providing respective C
capacitors are fully charged. Blanking the UV signals during the
C
the under-voltage threshold during normal operation. Cycling
the bias input power off then on resets the counter and the
fault latch.
Resistors (R
trip levels for each PWM converter. As shown in Figure 8, the
internal 200µA current sink (I
R
enables the overcurrent comparator (OVERCURRENT1 or
OVERCURRENT2). When the voltage across the upper
MOSFET (V
comparator trips to set the overcurrent latch. Both V
V
R
MOSFET switching. The overcurrent function will trip at a peak
inductor current (I
The OC trip point varies with MOSFET’s rDS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the ROCSET
resistor value from the equation above with:
I
PEAK
1. The maximum r
2. The minimum I
DS
SS
OCSET
OCSET
are referenced to V
charge interval allows the linear outputs to build above
0A
4V
2V
0V
=
1
0
I
--------------------------------------------------- -
(V
helps V
OCSET
FIGURE 7. OVERCURRENT OPERATION
SET
OCSET1
DS(ON)
T0
COUNT
r
DS ON
= 1
OVERLOAD
) that is referenced to V
T1
APPLIED
OCSET
×
PEAK)
(
R
) exceeds V
DS(ON)
OCSET
OCSET
and R
)
IN
determined by:
track the variations of V
T2
and a small capacitor across
OCSET2
at the highest junction temperature
from the specification table
OCSET
COUNT
SET
TIME
= 2
DISABLED
) program the overcurrent
, the overcurrent
) develops a voltage across
CHIP
IN
. The DRIVE signal
T3
IN
COUNT
= 3
due to
T4
SET
SS
and

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