ISL6559EVAL1 Intersil, ISL6559EVAL1 Datasheet - Page 12

• Manufacturer Part Number: ISL6559EVAL1
• Description: EVALUATION BOARD ISL6559
• Manufacturer: Intersil

Specifications of ISL6559EVAL1

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 1, Non-Isolated
• Power - Output: 125W
• Voltage - Output: 1.25V
• Current - Output: 100A
• Voltage - Input: 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6559, ISL6605
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Following the delay, the soft start ramps linearly until V
reaches VID. For the system described above, this first linear
ramp will continue for approximately
The final portion of the soft-start sequence is the time
remaining after V
zero. This is also characterized by a slight change in the slope
of the output voltage ramp which, for the current example,
exists for a time of
This behavior is seen in the example in Figure 9 of a converter
switching at 500kHz. For this converter, R
leading to T
and t
NOTE: Switching frequency 500kHz and R
Fault Monitoring and Protection
The ISL6559 actively monitors voltage and current feedback
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indication signal is provided for linking
to external system monitors. The schematic in Figure 10
t
t
DELAY
RAMP1
RAMP2
FIGURE 9. SOFT-START WAVEFORMS FOR ISL6559 BASED
RAMP2
=
=
=
=
=
-------------------------------------------------- -
1
T
---------- -
5.27ms
T
2.34ms
1.4
SS
SS
+
SS
= 1.17ms.
MULTI-PHASE BUCK CONVERTER
---------------------------------------- -
R
= 4.0ms, t
–
–
FB
t
DELAY
1.4 VID
t
RAMP
t
T
RAMP1
DELAY
160
SS
(
×
reaches VID and before I
t
10
RAMP1
DELAY
)
–
–
t
DELAY
6
=
12
560µs
= 700ns, t
t
RAMP2
FB
VOUT, 500mV/DIV
FB
RAMP1
EN, 5V/DIV
1ms/DIV
= 2.67kΩ
is set to 2.67kΩ
RAMP
= 2.23ms,
(EQ. 12)
(EQ. 10)
(EQ. 11
gets to
RAMP
ISL6559
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
which indicates that the converter is operating properly and
the output voltage is within a set window. The under-voltage
(UV) and over-voltage (OV) comparators create the output
voltage window. The controller also takes advantage of
current feedback to detect output over-current (OC)
conditions. PGOOD pulls low during shutdown and releases
high during soft-start once the output voltage exceeds the
UV threshold. Once high, PGOOD will only transition low
when the controller is disabled or a fault condition is
detected. It will return high under certain circumstances
once a fault clears.
Under-Voltage Protection
The voltage on V
is compared with the DAC reference voltage. By positively
offsetting the output voltage, an UV threshold is created
which moves relative to the VID code. During soft-start, the
slow rising output voltage eventually exceeds the UV
threshold. Assuming the POR leg of the PGOOD NOR gate
has not detected an OC fault, the PGOOD signal will go
high.
If a fault condition arises during operation and the output
voltage drops below the UV threshold, PGOOD will
immediately pull low, but converter operation will continue.
PGOOD will return high once the output voltage surpasses
the UV threshold.
If the ISL6559 is disabled during operation, the PGOOD
signal will not pull low until the output voltage decays below
the UV threshold.
VDIFF
FIGURE 10. POWER GOOD AND PROTECTION CIRCUITRY
REFERENCE
DAC
UV
2.2V
350mV
+
DIFF
-
+
-
OV
is internally offset by 350mV before it
CIRCUIT
POR
OC
December 29, 2004
+
-
FN9084.8
PGOOD
OVP
90µA
I
AVG