ISL6559EVAL1 Intersil, ISL6559EVAL1 Datasheet - Page 7

• Manufacturer Part Number: ISL6559EVAL1
• Description: EVALUATION BOARD ISL6559
• Manufacturer: Intersil

Specifications of ISL6559EVAL1

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 1, Non-Isolated
• Power - Output: 125W
• Voltage - Output: 1.25V
• Current - Output: 100A
• Voltage - Input: 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6559, ISL6605
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

To understand the reduction of ripple current amplitude in
the multi-phase circuit, examine the equation representing
an individual channel’s peak-to-peak inductor current.
In Equation 1, V
voltages respectively, L is the single-channel inductor value,
and f
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output-
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 36A to a 1.5V
load from a 12V input. The RMS input capacitor current is
5.9A. Compare this to a single-phase converter also
stepping down 12V to 1.5V at 36A. The single-phase
I
I
PP
C PP
,
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
=
S
=
(
----------------------------------------------------- -
V
is the switching frequency.
(
----------------------------------------------------------- -
IN
V
INPUT-CAPACITOR CURRENT, 10A/DIV
IN
–
L f
V
–
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
OUT
S
N V
L f
CHANNEL 1
INPUT CURRENT
10A/DIV
V
IN
S
IN
OUT
) V
V
and V
IN
OUT
CHANNEL 2
INPUT CURRENT
10A/DIV
) V
OUT
OUT
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
are the input and output
7
(EQ. 2)
(EQ. 1)
ISL6559
converter has 11.9A RMS input capacitor current. The
single-phase converter must use an input capacitor bank
with twice the RMS current capacity as the equivalent three-
phase converter.
Figures 15, 16 and 17 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution. Figure 18 shows the single
phase input-capacitor RMS current for comparison.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the ISL6559
is four. One switching cycle is defined as the time between
PWM1 pulse termination signals. The pulse termination
signal is an internally generated clock signal which triggers
the falling edge of PWM1. The cycle time of the pulse
termination signal is the inverse of the switching frequency
set by the resistor between the FS/DIS pin and ground. Each
cycle begins when the clock signal commands the channel-1
PWM output to go low. The PWM1 transition signals the
channel-1 MOSFET driver to turn off the channel-1 upper
MOSFET and turn on the channel-1 synchronous MOSFET.
In the default channel configuration, the PWM2 pulse
terminates 1/4 of a cycle after PWM1. The PWM 3 output
follows another 1/4 of a cycle after PWM2. PWM4 terminates
another 1/4 of a cycle after PWM3.
If PWM3 is connected to VCC, then two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle later.
Connecting PWM4 to VCC selects three channel operation
and the pulse-termination times are spaced in 1/3 cycle
increments.
Once a PWM signal transitions low, it is held low for a
minimum of 1/4 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
V
sawtooth ramp as illustrated in Figure 1. When the modified
V
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sensing
During the forced off time following a PWM transition low, the
controller senses channel load current by sampling the
voltage across the lower MOSFET r
ground-referenced amplifier, internal to the ISL6559,
connects to the PHASE node through a resistor, R
voltage across R
COMP
COMP
, minus the current correction signal relative to the
voltage crosses the sawtooth ramp, the PWM output
ISEN
is equivalent to the voltage drop
DS(ON)
, see Figure 3. A
December 29, 2004
ISEN
FN9084.8
. The