CDB4392 Cirrus Logic Inc, CDB4392 Datasheet
CDB4392
Specifications of CDB4392
Related parts for CDB4392
CDB4392 Summary of contents
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... DVD, SACD players, A/V receivers, CD and set-top box systems. The CS4392 is pin and register compatible with the CS4391, making easy performance upgrades possible. ORDERING INFORMATION CS4392-KS CS4392-KZ CS4392-KZZ, Lead Free - °C 20-pin TSSOP CDB4392 (SCL/CCLK) (AD0/CS) AMUTEC MODE SELECT ...
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TABLE OF CONTENTS 1. PIN DESCRIPTION - PCM DATA MODE .................................................................... 5 1.1 PIN DESCRIPTION - DSD mode ..................................................................... 6 2. TYPICAL CONNECTION DIAGRAMS ........................................................................ 7 3. APPLICATIONS ........................................................................................................... 9 3.1 Recommended Power-up Sequence for Hardware Mode ................................ 9 3.2 ...
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Soft Ramp or Zero Cross Enable (Bits 6:5) ...........................................20 6.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) .........................................20 6.3 Channel A Volume Control - Address 03h ......................................................22 6.4.1 Mute (Bit 7) ............................................................................................22 6.4.2 Volume Control (Bits 6:0) .......................................................................22 6.5 ...
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LIST OF FIGURES Figure 1. Typical Connection Diagram - PCM Mode....................................................................... 7 Figure 2. Typical Connection Diagram - DSD Mode ....................................................................... 8 Figure 3. CS4392 Output Filter ....................................................................................................... 9 Figure 4. Format 0, Left Justified up to 24-Bit Data....................................................................... 11 ...
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PIN DESCRIPTION - PCM DATA MODE (SCL/CCLK) M2 (SDA/CDIN) M1 (AD0/CS) M0 RST 1 Reset (Input) - Powers down device and resets all internal registers to their default settings Logic Power (Input) - Positive power for the ...
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PIN DESCRIPTION - DSD mode DSD_MODE DSD_SCLK (SCL/CCLK) M2 (SDA/CDIN) M1 (AD0/CS) M0 DSD_A 3 DSD Data (Input) - Input for Direct Stream Digital serial audio data. DSD_B 4 DSD_Mode 5 DSD Mode (Input stand alone mode, ...
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TYPICAL CONNECTION DIAGRAMS Mode Select (Control Port) * Logic Power +5V to 1.8V 0.1 µf Audio Data Processor * External Clock Figure 1. Typical Connection Diagram - PCM Mode * A high logic level for all digital inputs should ...
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Mode Select (Control Port) Logic Power +5V to 1.8V 0.1 µf Audio Data Processor * External Clock Figure 2. Typical Connection Diagram - DSD Mode * A high logic level for all digital inputs should not exceed VL ...
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... AC coupling capacitors to 2 caps per chan- nel. The circuit in figure 3 may also be DC coupled, however the filter on the CDB4392 must be AC coupled. The CS4392 is a linear phase design and does not include phase or amplitude compensation for an external filter ...
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Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS4392 incorpo- rates selectable interpolation filters for each mode of operation. A fast and a slow roll-off filter is available in each of Single, Double, and ...
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Digital Interface Format The device will accept audio samples in several digital interface formats as illustrated in Tables 5 and 8. The desired format is selected via the M0 and M1 pins for stand alone mode, and through the ...
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De-Emphasis The device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for F 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sam- ple rate Please see Table 5 ...
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... Also, use of the Mute Control function can enable the system de- signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute cir- cuit. See the CDB4392 data sheet for a suggested mute circuit. DS459PP3 64x oversampled DSD data with a 4x MCLK to DSD data rate ...
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CONTROL PORT INTERFACE The control port is used to load all the internal register settings (see section 6). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, ...
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I C Read To read from the device, follow the procedure below while adhering to the control port Switching Specifications. 1) Initiate a START condition to the I must be 001000. The seventh bit must match the setting ...
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SPI Mode In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 9 for the clock to data relationship). There is no AD0 pin. Pin CS is ...
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REGISTER QUICK REFERENCE Addr Function 7 01h Mode Control 1 AMUTE 1 02h Volume and MIxing Control 0 03h Channel A MUTE Volume Control 0 04h Channel B MUTE Volume Control 0 05h Mode Control 2 ...
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REGISTER DESCRIPTION ** All registers are read/write in Two-Wire mode and write only in SPI mode, unless otherwise noted** 6.1 Mode Control 1 - Address 01h 7 6 AMUTE DIF2 6.1.1 Auto-Mute (Bit 7) Function: The Digital-to-Analog converter output ...
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DSD Mode - The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital interface Format pins. Note that the Functional Mode registers must be set ...
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Volume and Mixing Control (Address 02h Soft Zero Cross 6.2.1 Channel A Volume = Channel B Volume (Bit 7) Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the ...
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ATAPI4 ATAPI3 ATAPI2 ...
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Channel A Volume Control - Address 03h See 4.4 Channel B Volume Control - Address 04h 6.4 CHANNEL B VOLUME CONTROL - ADDRESS 04H 7 6 MUTE VOL6 VOL5 6.4.1 Mute (Bit 7) Function: The Digital-to-Analog converter output will ...
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Control Port Enable (Bit 5) Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be accessed by setting this bit to 1. This will allow the operation of the ...
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Soft Volume Ramp-up after Reset (Bit 3) Function: This function allows the user to control whether a soft ramp up in volume is applied when reset is re- leased either by the reset pin or internal to the chip. ...
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CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (CS4392-KS/KZ/KZZ) specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth kHz; test load R = 3kΩ pF. Typical performance characteristics are derived ...
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) ...
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband Frequency Response kHz StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation De-emphasis Error (Relative to 1kHz) ...
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Frequency(normalized to Fs) Figure 12. Single Speed (fast) Stopband Rejection 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized ...
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Frequency(normalized to Fs) Figure 18. Single Speed (slow) Transition Band (detail 100 120 0.4 0.5 0.6 0.7 ...
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Frequency(normalized to Fs) Figure 24. Double Speed (slow) Stopband Rejection 0.45 0.46 0.47 0.48 0.49 0.5 0.51 ...
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Frequency(normalized to Fs) Figure 30. Quad Speed (fast) Transition Band (detail 100 120 0.1 0.2 0.3 0.4 ...
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SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE (Inputs: Logic Logic 1 = VL) . Parameters Input Sample Rate LRCK Duty Cycle MCLK Duty Cycle SCLK Frequency Quad Speed Mode (MCLKDIV=0) Quad Speed Mode (MCLKDIV=1) SCLK rising to ...
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SWITCHING SPECIFICATIONS - DSD INTERFACE Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Period DSD_L or DSD_R valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_L or DSD_R hold time ...
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SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (Inputs: logic 0 = AGND, logic 1 = VL) Parameter Mode SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first ...
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SWITCHING CHARACTERISTICS - SPI CONTROL PORT logic 1 = VL) Parameter SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time ...
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DC ELECTRICAL CHARACTERISTICS Parameter Normal Operation (Note 10) Power Supply Current Power Dissipation Power-Down Mode (Note 11) Power Supply Current Power Dissipation All Modes of Operation Power Supply Rejection Ratio (Note 12) Common Mode Voltage Output Impedance Maximum allowable DC ...
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RECOMMENDED OPERATING SPECIFICATIONS to AGND.) Parameters DC Power Supply ABSOLUTE MAXIMUM RATINGS Parameters DC Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature WARNING: Operation at or beyond these limits may ...
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... The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 9. REFERENCES 1. CDB4392 Evaluation Board Datasheet 2 2. “The I C-Bus Specification: Version 2.1” Philips Semiconductors, January 2000. ...
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DIMENSIONS 20L TSSOP (4.4 mm BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.03346 b 0.00748 D 0.252 E 0.248 E1 0.169 0.020 ∝ 0° Notes: ...
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PACKAGE DIMENSIONS 20L SOIC (300 MIL BODY) PACKAGE DRAWING 1 b SEATING PLANE DIM MIN A 0.093 A1 0.004 b 0.013 C 0.009 D 0.496 E 0.291 e 0.040 H 0.394 L 0.016 ∝ 0° 40 (cont.). D e INCHES ...