C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 120

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Comparator interrupts can be generated on rising-edge and/or falling-edge output transitions. (For inter-
rupt enable and priority control, see
Section “11.3. Interrupt Handler” on page 154
). The CP0FIF flag is
set upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set upon the Comparator0 rising-
edge interrupt. Once set, these bits remain set until cleared by software. The Output State of Comparator0
can be obtained at any time by reading the CP0OUT bit. Comparator0 is enabled by setting the CP0EN
bit to logic 1, and is disabled by clearing this bit to logic 0. Comparator0 can also be programmed as a
reset source; for details, see Section “
13.5. Comparator0 Reset
” on page
179
.
Note that after being enabled, there is a Power-Up time (listed in Table 10.1) during which the comparator
outputs stabilize. The states of the Rising-Edge and Falling-Edge flags are indeterminant after comparator
Power-Up and should be explicitly cleared before the comparator interrupts are enabled or the compara-
tors are configured as a reset source.
Comparator0 response time may be configured in software via the CP0MD1-0 bits in register CPT0MD
(see SFR Definition 10.2). Selecting a longer response time reduces the amount of current consumed by
Comparator0. See Table 10.1 for complete timing and current consumption specifications.
The hysteresis of each comparator is software-programmable via its respective Comparator control regis-
ter (CPT0CN and CPT1CN for Comparator0 and Comparator1, respectively). The user can program both
the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going sym-
metry of this hysteresis around the threshold voltage. The output of the comparator can be polled in soft-
ware, or can be used as an interrupt source. Each comparator can be individually enabled or disabled
(shutdown). When disabled, the comparator output (if assigned to a Port I/O pin via the Crossbar) defaults
to the logic low state, its interrupt capability is suspended and its supply current falls to less than 100 nA.
Comparator inputs can be externally driven from –0.25 V to (AV+) + 0.25 V without damage or upset.
Comparator0 hysteresis is programmed using bits 3-0 in the Comparator0 Control Register CPT0CN
(shown in SFR Definition 10.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in SFR Definition 10.1, the negative hysteresis can be programmed to three
different settings, or negative hysteresis can be disabled. In a similar way, the amount of positive hystere-
sis is determined by the setting the CP0HYP bits.
The operation of Comparator1 is identical to that of Comparator0, though Comparator1 may not be config-
ured as a reset source. Comparator1 is controlled by the CPT1CN Register (SFR Definition 10.3) and the
CPT1MD Register (SFR Definition 10.4). The complete electrical specifications for the Comparators are
given in Table 10.1.
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