C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 221

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

Bits7–6: Unused. Read = 00b. Write = don’t care.
Bit5:
Bit4:
Bits3–2: EMD1-0: EMIF Operating Mode Select.
Bits1–0: EALE1–0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
R/W
Bit7
-
PRTSEL: EMIF Port Select.
0: EMIF active on P0–P3.
1: EMIF active on P4–P7.
EMD2: EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-
chip memory space.
01: Split Mode without Bank Select: Accesses below the 8 k boundary are directed on-chip.
Accesses above the 8 k boundary are directed off-chip. 8-bit off-chip MOVX operations use
the current contents of the Address High port latches to resolve upper address byte. Note
that in order to access off-chip space, EMI0CN must be set to a page that is not contained in
the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 8 k boundary are directed on-chip.
Accesses above the 8k boundary are directed off-chip. 8-bit off-chip MOVX operations use
the contents of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the
CPU.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
SFR Definition 17.2. EMI0CF: External Memory Configuration
R/W
Bit6
-
PRTSEL
R/W
Bit5
EMD2
R/W
Bit4
Rev. 1.4
EMD1
R/W
Bit3
C8051F120/1/2/3/4/5/6/7
EMD0
R/W
Bit2
C8051F130/1/2/3
EALE1
R/W
Bit1
SFR Address:
SFR Page:
EALE0
R/W
Bit0
0xA3
0
00000011
Reset Value
221