C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 260

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Figure 19.2 shows a typical SMBus configuration. The SMBus0 interface will work at any voltage between
3.0 and 5.0 V and different devices on the bus may operate at different voltage levels. The bi-directional
SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high when the bus is free.
The maximum number of devices on the bus is limited only by the requirement that the rise and fall times
on the bus will not exceed 300 ns and 1000 ns, respectively.
19.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
19.2. SMBus Protocol
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. Note:
multiple master devices on the same bus are supported. If two or more masters attempt to initiate a data
transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitra-
tion. Note that it is not necessary to specify one device as the master in a system; any device who trans-
mits a START and a slave address becomes the master for that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is
received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see
Figure 19.3). If the receiving device does not ACK, the transmitting device will read a “not acknowledge”
(NACK), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address. The direction bit is set to
logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
260
VDD = 5V
1. The I2C-bus and how to use it (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor.
3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum.
Figure 19.2. Typical SMBus Configuration
VDD = 3V
Master
Device
Rev. 1.4
Device 1
VDD = 5V
Slave
VDD = 3V
Device 2
Slave
SDA
SCL