C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 288

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
21.1. UART0 Operational Modes
UART0 provides four operating modes (one synchronous and three asynchronous) selected by setting
configuration bits in the SCON0 register. These four modes offer different baud rates and communication
protocols. The four modes are summarized in Table 21.1.
21.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the
RX0 pin. The TX0 pin provides the shift clock for both transmit and receive. The MCU must be the master
since it generates the shift clock for transmission in both directions (see the interconnect diagram in
Figure 21.3).
Data transmission begins when an instruction writes a data byte to the SBUF0 register. Eight data bits are
transferred LSB first (see the timing diagram in Figure 21.2), and the TI0 Transmit Interrupt Flag
(SCON0.1) is set at the end of the eighth bit time. Data reception begins when the REN0 Receive Enable
bit (SCON0.4) is set to logic 1 and the RI0 Receive Interrupt Flag (SCON0.0) is cleared. One cycle after
the eighth bit is shifted in, the RI0 flag is set and reception stops until software clears the RI0 bit. An inter-
rupt will occur if enabled when either TI0 or RI0 are set.
The Mode 0 baud rate is SYSCLK / 12. RX0 is forced to open-drain in Mode 0, and an external pullup will
typically be required.
288
Mode
0
1
2
3
Synchronization
Asynchronous
Asynchronous
Asynchronous
Synchronous
RX (data out)
RX (data in)
TX (clk out)
TX (clk out)
Figure 21.2. UART0 Mode 0 Timing Diagram
Figure 21.3. UART0 Mode 0 Interconnect
C8051Fxxx
D0
Table 21.1. UART0 Modes
SYSCLK / 32 or SYSCLK / 64
D0
Timer 1, 2, 3, or 4 Overflow
Timer 1, 2, 3, or 4 Overflow
TX
RX
D1
D1
MODE 0 TRANSMIT
SYSCLK / 12
MODE 0 RECEIVE
Baud Clock
D2
Rev. 1.4
D2
D3
D3
CLK
DATA
D4
8 Extra Outputs
D4
D5
D5
Reg.
Shift
D6
Data Bits
D6
8
8
9
9
D7
D7
Start/Stop Bits
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
None