C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 313

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF1
R/W
Bit7
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 1 service routine if IT1 = 1. This flag is the inverse of the /INT1 signal.
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be falling-edge sensitive or
active-low.
0: /INT1 is level triggered, active-low.
1: /INT1 is edge triggered, falling-edge.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 0 service routine if IT0 = 1. This flag is the inverse of the /INT0 signal.
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be falling-edge sensitive or
active-low.
0: /INT0 is level triggered, active logic-low.
1: /INT0 is edge triggered, falling-edge.
TR1
R/W
Bit6
SFR Definition 23.1. TCON: Timer Control
TF0
R/W
Bit5
TR0
R/W
Bit4
Rev. 1.4
R/W
IE1
Bit3
C8051F120/1/2/3/4/5/6/7
R/W
IT1
Bit2
C8051F130/1/2/3
R/W
IE0
Bit1
SFR Address:
SFR Page:
R/W
IT0
Bit0
0x88
0
00000000
Addressable
Reset Value
Bit
313