C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 32

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.5.
The standard 8051 8-bit Ports (0, 1, 2, and 3) are available on the MCUs. The devices in the larger (100-
pin TQFP) packaging have 4 additional ports (4, 5, 6, and 7) for a total of 64 general-purpose port I/O. The
Port I/O behave like the standard 8051 with a few enhancements.
Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the "weak pullups"
which are normally fixed on an 8051 can be globally disabled, providing additional power saving capabili-
ties for low-power applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is a large digital switching network that
allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3. (See
Figure 1.11) Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are
supported.
The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion inputs, comparator out-
puts, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in
the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and
digital resources needed for the particular application.
32
Highest
Lowest
Priority
Priority
Latches
Port
Programmable Digital I/O and Crossbar
T2, T2EX,
/SYSCLK divided by 1,2,4, or 8
CNVSTR0/2
T4,T4EX
Comptr.
Outputs
UART0
SMBus
UART1
T0, T1,
/INT0,
/INT1
PCA
P0
P1
P2
P3
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0-P3.7)
8
8
8
8
2
4
2
2
7
2
8
2
Figure 1.11. Digital Crossbar Diagram
XBR2, P1MDIN
XBR0, XBR1,
Crossbar
Decoder
To External
Registers
Priority
Rev. 1.4
Digital
Interface
Memory
(EMIF)
8
8
8
8
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
Cells
Cells
Cells
Cells
To ADC2 Input
I/O
I/O
I/O
I/O
P0
P1
P2
P3
(‘F12x Only)
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Highest
Lowest
Priority
Priority