C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 321

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

Note:
Bit7:
Bit6:
Bit5–4:
Bit3:
Bit2:
Bit1:
Bit0:
SFR Address: TMR2CN:0xC8;TMR3CN:0xC8;TMR4CN:0xC8
SFR Page: TMR2CN: page 0;TMR3CN: page 1;TMR4CN: page 2
TFn
R/W
Bit7
TFn: Timer 2, 3, and 4 Overflow/Underflow Flag.
Set by hardware when either the Timer overflows from 0xFFFF to 0x0000, underflows from
the value placed in RCAPnH:RCAPnL to 0xFFFF (in Auto-reload Mode), or underflows from
0x0000 to 0xFFFF (in Capture Mode). When the Timer interrupt is enabled, setting this bit
causes the CPU to vector to the Timer interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
EXFn: Timer 2, 3, or 4 External Flag.
Set by hardware when either a capture or reload is caused by a high-to-low transition on the
TnEX input pin and EXENn is logic 1. When the Timer interrupt is enabled, setting this bit
causes the CPU to vector to the Timer Interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
Reserved.
EXENn: Timer 2, 3, and 4 External Enable.
Enables high-to-low transitions on TnEX to trigger captures, reloads, and control the direc-
tion of the timer/counter (up or down count). If DCENn = 1, TnEX will determine if the timer
counts up or down when in Auto-reload Mode. If EXENn = 1, TnEX should be configured as
a digital input.
0: Transitions on the TnEX pin are ignored.
1: Transitions on the TnEX pin cause capture, reload, or control the direction of timer count
(up or down) as follows:
Capture Mode: ‘1’-to-’0’ Transition on TnEX pin causes RCAPnH:RCAPnL to capture timer
value.
Auto-Reload Mode:
TRn: Timer 2, 3, and 4 Run Control.
This bit enables/disables the respective Timer.
0: Timer disabled.
1: Timer enabled and running/counting.
C/Tn: Counter/Timer Select.
0: Timer Function: Timer incremented by clock defined by TnM1:TnM0
(TMRnCF.4:TMRnCF.3).
1: Counter Function: Timer incremented by high-to-low transitions on external input pin.
CP/RLn: Capture/Reload Select.
This bit selects whether the Timer functions in capture or auto-reload mode.
0: Timer is in Auto-Reload Mode.
1: Timer is in Capture Mode.
Timer 3 and Timer 2 share the T2 and T2EX pins.
EXFn
SFR Definition 23.8. TMRnCN: Timer 2, 3, and 4 Control
R/W
Bit6
DCENn = 0: ‘1’-to-’0’ transition causes reload of timer and sets the EXFn Flag.
DCENn = 1: TnEX logic level controls direction of timer (up or down).
R/W
Bit5
-
R/W
Bit4
-
Rev. 1.4
EXENn
R/W
Bit3
C8051F120/1/2/3/4/5/6/7
TRn
R/W
Bit2
C8051F130/1/2/3
C/Tn
R/W
Bit1
CP/RLn 00000000
R/W
Bit0
Addressable
Reset Value
Bit
321