C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 55

• Manufacturer Part Number: C8051F120DK
• Description: DEVKIT-F120/21/22/23/24/25/26/27
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120, 121, 122, 123, 124, 125, 126, 127
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1224

5.
The ADC0 subsystem for the C8051F120/1/4/5 consists of a 9-channel, configurable analog multiplexer
(AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-regis-
ter ADC with integrated track-and-hold and Programmable Window Detector (see block diagram in
Figure 5.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable under
software control via the Special Function Registers shown in Figure 5.1. The voltage reference used by
ADC0 is selected as described in
(ADC0, track-and-hold and PGA0) is enabled only when the AD0EN bit in the ADC0 Control register
(ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
5.1.
Eight of the AMUX channels are available for external measurements while the ninth channel is internally
connected to an on-chip temperature sensor (temperature transfer function is shown in Figure 5.2). AMUX
input pairs can be programmed to operate in either differential or single-ended mode. This allows the user
to select the best measurement technique for each input channel, and even accommodates mode
changes "on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are two registers
associated with the AMUX: the Channel Selection register AMX0SL (SFR Definition 5.2), and the Configu-
ration register AMX0CF (SFR Definition 5.1). The table in SFR Definition 5.2 shows AMUX functionality by
channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount deter-
mined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (SFR Definition
5.3). The PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset.
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)
Analog Multiplexer and PGA
SENSOR
AGND
TEMP
AMX0CF
ADC0GTH
Figure 5.1. 12-Bit ADC0 Functional Block Diagram
+
+
+
+
-
-
-
-
AMUX
(SE or
9-to-1
DIFF)
AMX0SL
ADC0GTL
Section “9. Voltage Reference” on page 113
X
+
-
AV+
AD0EN
AGND
ADC0CF
Rev. 1.4
ADC0LTH
C8051F120/1/2/3/4/5/6/7
ADC
12-Bit
AV+
SAR
ADC0CN
ADC0LTL
C8051F130/1/2/3
Start Conversion
12
24
. The ADC0 subsystem
Comb.
00
01
10
11
12
Logic
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
AD0WINT
55