DEV TOOL EZDSP USB STICK C5505

TMDX5505EZDSP

Manufacturer Part NumberTMDX5505EZDSP
DescriptionDEV TOOL EZDSP USB STICK C5505
ManufacturerTexas Instruments
SeriesCode Composer Studio™ IDE and eXpressDSP™
TypeDSP
TMDX5505EZDSP datasheet
 


Specifications of TMDX5505EZDSP

ContentsBoard, CDArchitectureDSP
Ide IncludedCode Composer CCSCode Gen Tools IncludedCode Composer CCS
Debugger IncludedCode Composer CCSProcessor To Be EvaluatedTMS320VC5504
Data Bus Width16 bitInterface TypeUSB
Silicon ManufacturerTexas InstrumentsCore ArchitectureC5000
Core Sub-architectureTMS320C55xSilicon Core NumberTMS320VC
Silicon Family NameTMS320VC5xxxKit ContentsBoard
For Use With/related ProductsTMS320VC5504, TMS320VC5505Lead Free Status / RoHS StatusLead free by exemption / RoHS compliant by exemption
Other names296-24965  
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1 Fixed-Point Digital Signal Processor
1.1
TMS320VC5505 Features
1
• High-Performance, Low-Power, TMS320C55x™
Fixed-Point Digital Signal Processor
– 16.67-, 10-ns Instruction Cycle Time
– 60-, 100-MHz Clock Rate
– One/Two Instruction(s) Executed per Cycle
– Dual Multipliers [Up to 200 Million
Multiply-Accumulates per Second (MMACS)]
– Two Arithmetic/Logic Units (ALUs)
– Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write Buses
– Fully Software-Compatible With C55x
Devices
– Industrial Temperature Devices Available
• 320 K Bytes Zero-Wait State On-Chip RAM,
Composed of:
– 64K Bytes of Dual-Access RAM (DARAM),
8 Blocks of 4K x 16-Bit
– 256K Bytes of Single-Access RAM (SARAM),
32 Blocks of 4K x 16-Bit
• 128K Bytes of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit)
• 16-/8-Bit External Memory Interface (EMIF) with
Glueless Interface to:
– 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
– 8-/16-Bit NOR Flash
– Asynchronous Static RAM (SRAM)
• Direct Memory Access (DMA) Controller
– Four DMA With 4 Channels Each
(16-Channels Total)
• Three 32-Bit General-Purpose Timers
– One Selectable as a Watchdog and/or GP
• Two MultiMedia Card/Secure Digital (MMC/SD)
Interfaces
• Universal Asynchronous Receiver/Transmitter
(UART)
• Serial-Port Interface (SPI) With Four
Chip-Selects
• Master/Slave Inter-Integrated Circuit (I
2
• Four Inter-IC Sound (I
S Bus™) for Data
Transport
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TMS320VC5505
Fixed-Point Digital Signal Processor
Check for Samples:
TMS320VC5505
• Device USB Port With Integrated 2.0
High-Speed PHY that Supports:
– USB 2.0 Full- and High-Speed Device
• LCD Bridge With Asynchronous Interface
• Tightly-Coupled FFT Hardware Accelerator
• 10-Bit 4-Input Successive Approximation (SAR)
ADC
• Real-Time Clock (RTC) With Crystal Input, With
Separate Clock Domain, Separate Power
Supply
• Four Core Isolated Power Supply Domains:
Analog, RTC, CPU and Peripherals, and USB
• Four I/O Isolated Power Supply Domains: RTC
I/O, EMIF I/O, USB PHY, and DV
• Low-Power S/W Programmable Phase-Locked
Loop (PLL) Clock Generator
• On-Chip ROM Bootloader (RBL) to Boot From
NAND Flash, NOR Flash, SPI EEPROM, or I2C
EEPROM
• IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
• Up to 26 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
• 196-Terminal Pb-Free Plastic BGA (Ball Grid
Array) (ZCH Suffix)
• 1.05-V Core (60 MHz), 1.8-V, 2.5-V, 2.8-V, or
3.3-V I/Os
• 1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.8-V, or
3.3-V I/Os
• Applications:
– Wireless Audio Devices (e.g., Headsets,
Microphones, Speakerphones, etc.)
– Echo Cancellation Headphones
– Portable Medical Devices
– Voice Applications
– Industrial Controls
– Fingerprint Biometrics
– Software Defined Radio
2
C Bus™)
• Community Resources
TI E2E Community
TI Embedded Processors Wiki
TMS320VC5505
SPRS503B – JUNE 2009 – REVISED JANUARY 2010
DDIO
Copyright © 2009–2010, Texas Instruments Incorporated

TMDX5505EZDSP Summary of contents

  • Page 1

    ... Voice Applications – Industrial Controls – Fingerprint Biometrics – Software Defined Radio 2 C Bus™) • Community Resources – TI E2E Community – TI Embedded Processors Wiki TMS320VC5505 SPRS503B – JUNE 2009 – REVISED JANUARY 2010 DDIO Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 2

    ... Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs. The VC5505 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™ ...

  • Page 3

    ... I S (x4) (x4) App-Spec Display 10-Bit LCD SAR Bridge ADC Figure 1-1. TMS320VC5505 Functional Block Diagram Copyright © 2009–2010, Texas Instruments Incorporated DSP System C55x™ DSP CPU JTAG Interface FFT Hardware PLL/Clock Accelerator Generator 64 KB DARAM Power Management 256 KB SARAM ...

  • Page 4

    ... USB_MXI Pins ......................................... Clock PLLs ........... Direct Memory Access (DMA) Controller ............................................... Reset ............... Wake-up Events, Interrupts, and XF ................. External Memory Interface (EMIF) ............................. ........................ .............................................. (UART) ................................ ......... ......................... .......................... .................... ................................ ............................................ ............................. Thermal Data for ZCH ............................ Packaging Information Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com ........ 104 114 ........ 117 124 126 130 132 132 ...

  • Page 5

    ... Section 6.8.2 Table 6-9 Wake-Up From IDLE Switching Characteristics Over Recommended Operating Conditions For Wake-Up From IDLE Electrical Data/Timing • Added footnote that references LDO. Copyright © 2009–2010, Texas Instruments Incorporated ADDITIONS/MODIFICATIONS/DELETIONS , USB_V , and USB_V DDPLL DDOSC , USB_V , and USB_V ...

  • Page 6

    ... V, 60 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz 0.14 mW/MHz @ 1. MHz 0.22 mW/MHz @ 1.3 V, 100 MHz 0.25 mW/MHz @ 1. MHz 0.31 mW/MHz @ 1.3 V, 100 MHz Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com VC5505 2 MMC/SD ...

  • Page 7

    ... I/O space. The VC5505 includes three types of on-chip memory: 128 KB read-only memory (ROM), 256 KB single-access random access memory (SARAM dual-access random access memory (DARAM). The memory map is shown in Copyright © 2009–2010, Texas Instruments Incorporated Figure Submit Documentation Feedback ...

  • Page 8

    ... Product Folder Link(s): TMS320VC5505 www.ti.com MEMORY BLOCK (1) DARAM 0 DARAM 1 DARAM 2 DARAM 3 DARAM 4 DARAM 5 DARAM 6 DARAM 7 Figure 3-1 , MEMORY BLOCK SARAM 0 SARAM 1 SARAM 2 SARAM 3 SARAM 4 SARAM 5 SARAM 6 SARAM 7 SARAM 8 SARAM 9 SARAM 10 SARAM 11 SARAM 12 SARAM 13 SARAM 14 SARAM 15 Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 9

    ... To maximize power savings, the I/O pin of the EMIF can be operated at an independent voltage from the rest of other I/O pins on the device. Copyright © 2009–2010, Texas Instruments Incorporated Table 3-3. SARAM Blocks (continued) ...

  • Page 10

    ... Idle Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved System Control Reserved Reserved Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com DMA0 DMA1 DMA2 DMA3 EMIF Timer0 Timer1 Timer2 RTC I2C ...

  • Page 11

    ... Copyright © 2009–2010, Texas Instruments Incorporated PERIPHERAL Reserved Reserved MMC/SD0 Reserved MMC/SD1 Reserved SAR and Analog Control Registers ...

  • Page 12

    ... Product Folder Link(s): TMS320VC5505 www.ti.com BLOCK SIZE 64K Minus 192 Bytes 256K Bytes 8M Minus 320K Bytes 4M Bytes Asynchronous 2M Bytes Asynchronous 1M Bytes Asynchronous 1M Minus 128K Bytes Asynchronous 128K Bytes Asynchronous (if MPNMC=1) 128K Bytes ROM (if MPNMC=0) Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 13

    ... DDEMIF Shading denotes pins not supported on this device. To ensure proper device operation, these pins must be hooked up properly, see Table 3-19, Regulators and Power Management Terminal Functions. Copyright © 2009–2010, Texas Instruments Incorporated LCD_ LCD_D[0]/ LCD_D[2]/ LCD_D[5]/ RW_WRB/ DV SPI_RX GP[12] DDIO ...

  • Page 14

    ... For proper device operation, external pullup/pulldown resistors may be required on some pins. Section 4.8.1, Pullup/Pulldown Resistors discusses situations where external pullup/pulldown resistors are required. 14 Device Overview (Table 3-5 through Table 3-22) identify the external signal names, the Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 15

    ... IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see (3) Specifies the operating I/O supply voltage for each signal Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap different clocks within the DSP clock generator ...

  • Page 16

    ... RTC alarm. Section 4.8.1 , Pullup/Pulldown Resistors. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com DESCRIPTION ). A voltage must still be applied DDRTC ). A voltage must still be applied DDRTC voltage. The DDRTC Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 17

    ... I = Input Output High impedance Supply voltage, GND = Ground Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see (3) Specifies the operating I/O supply voltage for each signal Copyright © 2009–2010, Texas Instruments Incorporated (1) (2) (3) OTHER RESET External Flag Output ...

  • Page 18

    ... The IPU resistor on these pins can be enabled or disabled via the DV DDIO PDINHIBR2 register. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com DESCRIPTION is required to provide a signal rise time of DDIO is required to provide a signal rise time of DDIO Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 19

    ... IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see (3) Specifies the operating I/O supply voltage for each signal Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) Note: When accessing 8-bit Asynchronous memory, pins EM_A[20:0] should be connected to memory address pins [22:2] and EM_BA[1:0] should be connected to memory addresss pins [1:0] ...

  • Page 20

    ... DDEMIF EMIF wait state extension input 4 for EM_CS4 DDEMIF EMIF wait state extension input 3 for EM_CS3 DDEMIF EMIF wait state extension input 2 for EM_CS2 DDEMIF Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 21

    ... IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see (3) Specifies the operating I/O supply voltage for each signal Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) I2C This pin is the I2C clock output. Per the I2C standard, an external pullup is required ...

  • Page 22

    ... For I2S I2S3 frame synchronization input/output I2S3_FS. DV Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be DDIO enabled or disabled via the PDINHIBR3 register. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 23

    ... IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see (3) Specifies the operating I/O supply voltage for each signal Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) Serial Port Interface (SPI) This pin is multiplexed between LCD Bridge and SPI ...

  • Page 24

    ... When the USB peripheral is not used, the USB_R1 signal should be connected via a 10-kΩ resistor to USB_V SSREF Section 4.8.1 , Pullup/Pulldown Resistors. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 DESCRIPTION DESCRIPTION should be connected to ground DDOSC and be placed as close to the device as SSREF . Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com ...

  • Page 25

    ... S Section DDPLL USB_V G11 GND Section SSPLL Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to see USB_R1. 5.2, When the USB peripheral is not used, the USB_V ROC directly to ground (V ) ...

  • Page 26

    ... For LCD Bridge LCD data pin 7. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be DDIO enabled or disabled via the PDINHIBR3 register. Section 4.8.1 , Pullup/Pulldown Resistors. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 27

    ... SPI_TX LCD_D[0]/ P6 I/O/Z DV SPI_RX Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) DESCRIPTION This pin is multiplexed between LCD Bridge and GPIO. IPD For LCD Bridge LCD data pin 6. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be DDIO enabled or disabled via the PDINHIBR3 register ...

  • Page 28

    ... Mux control via the SP0MODE bits in the EBSR. DV DDIO The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1 register. IPD DV DDIO Section 4.8.1 , Pullup/Pulldown Resistors. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com DESCRIPTION DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 29

    ... IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see (3) Specifies the operating I/O supply voltage for each signal Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) SAR ADC GPAIN0: General -Purpose Output and Analog Input pin 0. This pin is demuxed internally into ADC Channels 0, 1, & ...

  • Page 30

    ... Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be DDIO enabled or disabled via the PDINHIBR1 register. Section 4.8.1 , Pullup/Pulldown Resistors. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 31

    ... EM_A[19]/GP[25] G4 I/O/Z EM_A[20]/GP[26] J3 I/O/Z Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) This pin is multiplexed between LCD Bridge and GPIO. IPD For GPIO general-purpose input/output pin 12 (GP[12]). DV Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be DDIO enabled or disabled via the PDINHIBR3 register ...

  • Page 32

    ... For GPIO general-purpose input/output pin 31 (GP[31]). DV Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be DDIO enabled or disabled via the PDINHIBR3 register. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 33

    ... IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see (3) Specifies the operating I/O supply voltage for each signal Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) Regulators [Not supported on this device. Reserved for compatibility with future devices]. ...

  • Page 34

    ... Digital Core supply voltage (60 MHz) 1.3-V Digital Core supply voltage (100 MHz) 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/O power supply for non-EMIF and non-RTC I/Os Section 4.8.1 , Pullup/Pulldown Resistors. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com DESCRIPTION . DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 35

    ... IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see (3) Specifies the operating I/O supply voltage for each signal Copyright © 2009–2010, Texas Instruments Incorporated (2) (3) 1.8-V, 2.5-V, 2.8-V, or 3.3-V EMIF I/O power supply 1 ...

  • Page 36

    ... Instruments web site on the Worldwide Web at information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 36 Device Overview http://www.ti.com Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com uniform resource locator (URL). For ...

  • Page 37

    ... TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used ...

  • Page 38

    ... DMA2 Channel Event Source Register 1 DMA2 Channel Event Source Register 2 DMA3 Channel Event Source Register 1 DMA3 Channel Event Source Register 2 Peripheral Clock Stop Request/Acknowledge Register USB LDO Control Register Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com COMMENTS see Section 4 ...

  • Page 39

    ... RTCLKOUT and WAKEUP pins. To disable the RTC oscillator, connect the RTC_XI pin to CV For more information on crystal specifications for the RTC oscillator and the USB oscillator, see Section 6.4, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins. Copyright © 2009–2010, Texas Instruments Incorporated and V ) DDA_ANA DDA_PLL ...

  • Page 40

    ... USB oscillator stabilizes before proceeding with the USB configuration. The USB oscillator stabilization time is 100 ms, typically with maximum (Note: the startup time is highly dependent on the ESR and capacitive load on the crystal). 40 Device Configuration 6.5, Clock PLLs. Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 41

    ... Enable TIMER0 to start counting 200 ms. 18. Ensure a minimum of 200 ms has elapsed since step 17 before proceeding to execute the bootloaded code. 19. Jump to the entry point specified in the boot image. Copyright © 2009–2010, Texas Instruments Incorporated Section 6.7, Reset. Figure 4-1 ). For more information on the boot modes supported, see ...

  • Page 42

    ... Memory MMC/SD0 Boot (Not Supported) ? Start Timer0 to Count 200 ms UART Boot (Not Supported) ? Has Timer0 USB Boot Counter Expired (Not Supported Yes Jump to Stored Execution Point Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com No Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 43

    ... The Bootloader uses SARAM block 31 for the storing of temporary data. This block of memory is reserved during the boot process. However, after the boot process is complete, it can be used by the user application. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ...

  • Page 44

    ... DSP clock generator while CLKIN is ignored CLKIN drives the DSP clock generator and the 32-KHz on-chip oscillator drives only the RTC timer. This pin is not allowed to change during device operation; it must be tied high or low at the board. Section Copyright © 2009–2010, Texas Instruments Incorporated 4.7, ...

  • Page 45

    ... Mode 1 (I2S1 and GP[11:10]). 4 signals of the I2S1 module and 2 GP[11:10] signals are routed to the 6 external signals of the serial port Mode 2 (GP[11:6]). 6 GPIO signals (GP[11:6]) are routed to the 6 external signals of the serial port Reserved. Copyright © 2009–2010, Texas Instruments Incorporated 12 11 PPMODE R/W-00 ...

  • Page 46

    ... The peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable the peripheral clocks. 46 Device Configuration DESCRIPTION Section 4.7.1.3, MMC0, I2S0, and GP[5:0] Pin Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Table 4-6, ...

  • Page 47

    ... Thus, the drive strength is ultimately the same strength. The slower slew rate control can be used for power savings and has the greatest effect at lower VDD_IO voltages. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ...

  • Page 48

    ... The LCD Controller, SPI, UART, I2S2, I2S3, and GPIO signal muxing is determined by the value of the PPMODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 4-4 48 Device Configuration . Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 49

    ... LCD_D[15]/UART_TXD/GP[31]/I2S3_DX LCD_CS0_E0/SPI_CS0 LCD_CS1_E1/SPI_CS1 LCD_RW_WRB/SPI_CS2 LCD_RS/SPI_CS3 (1) The pin mux signals names with PDINHIBR3 register bit field references can have the pulldown resister enabled or disabled via this register. Copyright © 2009–2010, Texas Instruments Incorporated EBSR PPMODE BITS MODE 0 MODE 1 MODE 2 000 ...

  • Page 50

    ... PIN MUX MODE 0 00 MMC1_CLK MMC1_CMD MMC1_D0 MMC1_D1 MMC1_D2 MMC1_D3 Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com EBSR SP1MODE BITS MODE 1 MODE I2S1_CLK GP[6] I2S1_FS GP[7] I2S1_DX GP[8] I2S1_RX GP[9] GP[10] GP[10] GP[11] GP[11] Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 51

    ... Pins). Note that some configuration pins must connected directly to ground specific supply voltage. • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. Copyright © 2009–2010, Texas Instruments Incorporated MODE 0 00 MMC0_CLK MMC0_CMD ...

  • Page 52

    ... Device Configuration Table 4-2, Default Functions Affected by Device Configuration Pins and the low-/high-level input voltages (V I 5.3, Electrical Characteristics Over Recommended Ranges of Supply Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com rail. DD and V ...

  • Page 53

    ... V @ 100 MHz for commercial temperature, the Device Operating Life Power-On Hours are 70, 000 DD POH of the total POH . For devices running with 100 MHz for industrial temperature, the Device Operating Life Power-On Hours are 17, 000 DD POH of the total POH. Copyright © 2009–2010, Texas Instruments Incorporated Digital Core ( USB_V DD DDRTC DD1P3 I/O, 1 ...

  • Page 54

    ... 0 -0.3 0 -0.3 3.6 -0 0.3 DDA_ANA 100 Section 3.5 , Terminal Functions. Copyright © 2009–2010, Texas Instruments Incorporated UNIT °C °C MHz MHz ...

  • Page 55

    ... Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. (8) When the ANA_LDO supplies V DDA_ANA The I parameter of the ANA_LDO is too low to drive any realistic load on the GPAIN[3:1] pins while also supplying the PLL through SD V and the SAR through V DDA_PLL DDA_ANA Copyright © 2009–2010, Texas Instruments Incorporated (1) TEST CONDITIONS > ...

  • Page 56

    ... DDA_ANA Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com MIN TYP MAX + -10 +10 -10 +10 0.22 mW/MHz 0.15 mW/MHz 0.22 mW/MHz 0.14 mW/MHz 0.31 mW/MHz 0.25 mW/MHz 0.44 0.26 0.40 0.23 0.28 0.15 0.7 1 Copyright © 2009–2010, Texas Instruments Incorporated UNIT ...

  • Page 57

    ... Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. 6.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between V manner. Copyright © 2009–2010, Texas Instruments Incorporated Tester Pin Electronics Transmission Line (see Note) MAX and V ...

  • Page 58

    ... V DDA_ANA , USB_V , and USB_V DDA3P3 DDPLL , and USB_V ) should not ramp DDA3P3 DDPLL , USB_V ) reach 0.9 V. DDA1P3 , USB_V ) and USB PHY and I/O level DDA1P3 Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com ), and ), and . DDA_PLL DDA_PLL . , DDOSC , DD1P3 , DD1P3 ...

  • Page 59

    ... may be connected to a different supply that meets the recommended operating DD conditions (see Section 5.2), if desired. Copyright © 2009–2010, Texas Instruments Incorporated supply (1.8-, 2.5-, 2.8-, or 3.3-V). DDIO Section 6.4.1, Real-Time Clock (RTC) On-Chip Oscillator With Section 6.4.3, USB On-Chip Oscillator With External Figure 6-3 ...

  • Page 60

    ... The load capacitors, C1 and C2, are the total capacitance SSRTC (1) Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com 1.05/1.3 V pin. MIN NOM MAX UNIT 0.2 2 sec 32.768 kHz 100 kΩ 1.6 pF 1.0 mW Figure 6-4 and Figure Copyright © 2009–2010, Texas Instruments Incorporated 6-5. ...

  • Page 61

    ... The USB on-chip oscillator can be permanently disabled, via tie-offs, if the USB peripheral is not being used. To permanently disable the USB oscillator, connect the USB_MXI pin to ground (V USB_MXO pin unconnected. The USB oscillator power pins (USB_V be connected to ground. Copyright © 2009–2010, Texas Instruments Incorporated Section RTC_XI RTC_XO ...

  • Page 62

    ... SPRS503B – JUNE 2009 – REVISED JANUARY 2010 USB_MXI Crystal 12 MHz C1 62 Peripheral Information and Electrical Specifications USB_MXO USB_V USB_V SSOSC DDOSC C2 3.3 V Figure 6-6. 12-MHz USB Oscillator Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com V USB_V SS DDA3P3 3.3 V Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 63

    ... Table 6-3. PLLC1 Clock Frequency Ranges CLOCK SIGNAL NAME (1) CLKIN RTC Clock PLLIN PLLOUT SYSCLK PLL_LOCKTIME (1) These CLKIN values are used when the CLK_SEL pin = 1. Copyright © 2009–2010, Texas Instruments Incorporated Table 6-2. The load capacitors, C1 and C2 are the total capacitance MIN ( 1. MIN MAX MIN 11 ...

  • Page 64

    ... Figure 6-7. CLKIN Timing Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Section 5.3, Electrical Characteristics Section 6.5.3, Clock (see Figure 6- 1 MIN NOM MAX 88.577, 83.333 81.380 0.466 * t c(CLKIN) 0.466 * t c(CLKIN) 0. c(CLKIN) MIN Copyright © 2009–2010, Texas Instruments Incorporated UNIT ...

  • Page 65

    ... P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use ns. (3) Transition time is measured with the slew rate set to FAST and DV Output Slew Rate Control Register (OSRCR) [1C16h].). CLKOUT Copyright © 2009–2010, Texas Instruments Incorporated (see Figure 6-8) ...

  • Page 66

    ... Synchronization events are selected by programming the CHnEVT field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2). 66 Peripheral Information and Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com ...

  • Page 67

    ... DSP_LDOO entry in Table pin floating, the VC5505 's internal circuits provide the necessary voltage above the POR's threshold for POWERGOOD. Copyright © 2009–2010, Texas Instruments Incorporated and resets the RTC registers when power is first applied DD_RTC DD_RTC 3-19, Regulators and Power Management Terminal Functions. By leaving this ...

  • Page 68

    ... SYNCH 0→1 Group: LCD_CS0_E0/SPI_CS0, LCD_RW_WRB/SPI_CS2, RSV13 • SYNCH 1→0 Group: RSV10, RSV11 • SYNCH X→1 Group: EM_BA[1:0] • SYNCH X→0 Group: EM_A[20:0] • 68 Peripheral Information and Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com ...

  • Page 69

    ... SYNCH 0 1 → Group SYNCH 1 0 → Group CLKOUT Figure 6-9. Power-On Reset Timing Requirements Copyright © 2009–2010, Texas Instruments Incorporated (1) (see Figure 6-9 CV 64k + 8 clocks if CLK_SEL = clocks if CLK_SEL = 0 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): ...

  • Page 70

    ... Group SYNCH 0 1 → Group SYNCH 1 0 → Group CLKOUT 70 Peripheral Information and Electrical Specifications Figure 6-10. Reset Timing Requirements Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 64k + 8 clocks if CLK_SEL = clocks if CLK_SEL = 0 Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com ...

  • Page 71

    ... P = 1/SYSCLK clock frequency in ns. For example, when running parts at 100 MHz ns. ( 1/RTCCLK= 30.5 ms. RTCCLK is the clock output of the 32.768-kHz RTC oscillator. (3) Assumes the internal LDOs are used with a 0.1uF bandgap capacitor. Copyright © 2009–2010, Texas Instruments Incorporated 1 2 Figure 6-11. External Interrupt Timings ...

  • Page 72

    ... Peripheral Information and Electrical Specifications 2 1 Figure 6-12. Wake-Up From IDLE Timings (see Figure 6-13) PARAMETER 1 Figure 6-13. XF Timings Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com ( MIN MAX 0 10.2 Section 4.6.1, External Bus Copyright © 2009–2010, Texas Instruments Incorporated UNIT ns ...

  • Page 73

    ... NCS4ECC1 (1) Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable word accesses to the EMIF registers. Copyright © 2009–2010, Texas Instruments Incorporated REGISTER NAME Revision Register Status Register Asynchronous Wait Cycle Configuration Register 1 ...

  • Page 74

    ... NAND Flash 4-Bit ECC Error Value Register 1 NAND Flash 4-Bit ECC Error Value Register 2 NAND Flash 4-Bit ECC Error Value Register 3 NAND Flash 4-Bit ECC Error Value Register 4 Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www ...

  • Page 75

    ... Figure 6-16 and Figure 6-17 phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. Copyright © 2009–2010, Texas Instruments Incorporated = 1. 3.3/2.8/2.5/1 DDEMIF ...

  • Page 76

    ... Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 77

    ... Output setup time, EM_D[15:0] valid to EM_WE low su(EMDV-EMWEL Output hold time, EM_WE high to EM_D[15:0] invalid h(EMWEH-EMDIV) 6.9.4 EMIF Electrical Data/Timing CV DD Copyright © 2009–2010, Texas Instruments Incorporated (3) Figure 6-17 ) (continued) MIN (WST)*E-9 (WST+(EWC*16))*E-9 (WS)*E-9 (WH)*E 3.3/2.8/2.5/1.8 V ...

  • Page 78

    ... WRITES describe EMIF transactions that include extended wait states inserted during the STROBE Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com (1) (see Figure 6-14, Figure 6-16, and 3.3/2.8/2.5/1.8 V DDEMIF MIN NOM MAX ( ( Copyright © 2009–2010, Texas Instruments Incorporated UNIT ...

  • Page 79

    ... EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. Copyright © 2009–2010, Texas Instruments Incorporated Figure ...

  • Page 80

    ... Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com (1) (2) (3) (see Figure 6- 1 3.3/2.8/2.5/1.8 V DDEMIF NOM MAX (WST)*E (WST)*E+5 (WST+(EWC*16))*E (WST+(EWC*16))*E+5 4E 4E+5 (WS)*E (WS)*E+5 (WH)*E (WH)*E+5 Copyright © 2009–2010, Texas Instruments Incorporated , UNIT ...

  • Page 81

    ... EM_CS[5:2] EM_BA[1:0] EM_A[20: EM_WE 24 EM_D[15:0] EM_OE Figure 6-15. Asynchronous Memory Write Timing for EMIF Copyright © 2009–2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 TMS320VC5505 SPRS503B – JUNE 2009 – REVISED JANUARY 2010 ...

  • Page 82

    ... Figure 6-17. EM_WAITx Write Timing Requirements 82 Peripheral Information and Electrical Specifications S ROBE T Extended Due to EM_WAITx Asserted Deasserted STROBE Extended Due to EM_WAITx Asserted Deasserted Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com S ROBE T HOLD STROBE HOLD ...

  • Page 83

    ... MMC/SD Peripheral Register Description(s) Table 6-16 and Table 6-17 0x3A00 and the MMC/SD1 registers start at address 0x3B00. Copyright © 2009–2010, Texas Instruments Incorporated shows the MMC/SD registers. The MMC/SD0 registers start at address Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): ...

  • Page 84

    ... MMC Response Register 3 MMC Response Register 4 MMC Response Register 5 MMC Response Register 6 MMC Response Register 7 MMC Data Response Register MMC Command Index Register Reserved MMC FIFO Control Register Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com ...

  • Page 85

    ... MMCRSP7 3B48h MMCDRSP 3B50h MMCCIDX 3B74h MMCFIFOCTL Copyright © 2009–2010, Texas Instruments Incorporated Table 6-17. MMC/SD1 Registers REGISTER NAME MMC Control Register MMC Memory Clock Control Register MMC Status Register 0 MMC Status Register 1 MMC Interrupt Mask Register MMC Response Time-Out Register ...

  • Page 86

    ... Product Folder Link(s): TMS320VC5505 Figure 6-18 and Figure 6- FAST MODE STD MODE MIN MAX MIN MAX 1 1. FAST MODE STD MODE MIN MAX MIN MAX ( 400 0 400 End Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com UNIT (1) (see UNIT (2) MHz kHz ...

  • Page 87

    ... MMCx_CLK START MMCx_CMD MMCx_CLK 16 MMCx_DAT Copyright © 2009–2010, Texas Instruments Incorporated XMIT Valid Valid Figure 6-20. MMC/SD Host Write Timing 7 VALID Figure 6-21. MMC/SD Data Write Timing Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 TMS320VC5505 SPRS503B – ...

  • Page 88

    ... Peripheral Information and Electrical Specifications power pin. The RTC flops are not reset by the device's DD_RTC Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Table 6-20) ...

  • Page 89

    ... RTCSCR4 6.11.1.1 RTC Electrical Data/Timing For more detailed information on RTC electrical timings, specifically WAKEUP, see the Reset Electrical Data/Timing. Copyright © 2009–2010, Texas Instruments Incorporated REGISTER NAME RTC Interrupt Enable Register RTC Update Register Milliseconds Register Milliseconds Alarm Register ...

  • Page 90

    ... SCL pins suppress noise that has a duration shorter. The I2C module clock is derived from the DSP clock divided by a programmable prescaler. 90 Peripheral Information and Electrical Specifications 2 C-bus™) specification version 2.1. External Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com ...

  • Page 91

    ... ICEMDR 1A30h ICPSC 1A34h ICPID1 1A38h ICPID2 Copyright © 2009–2010, Texas Instruments Incorporated REGISTER NAME I2C Own Address Register I2C Interrupt Mask Register I2C Interrupt Status Register I2C Clock Low-Time Divider Register I2C Clock High-Time Divider Register I2C Data Count Register ...

  • Page 92

    ... SCL signal) to bridge the IHmin ] of the SCL signal. w(SCLL) Copyright © 2009–2010, Texas Instruments Incorporated UNIT µs µs µs µs µs ns (4) µs µ µs ...

  • Page 93

    ... If mixed with HS-mode devices, faster fall-times are allowed. b (2) The rise/fall times are measured at 30% and 70 external pullup resistor. However, the rise time (t The pullup resistor must be selected to meet the I2C rise and fall time values specified. Copyright © 2009–2010, Texas Instruments Incorporated Figure 6-22 ...

  • Page 94

    ... SPRS503B – JUNE 2009 – REVISED JANUARY 2010 26 SDA 23 25 SCL 16 18 Stop Start 94 Peripheral Information and Electrical Specifications Repeated Start Figure 6-23. I2C Transmit Timings Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Stop Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 95

    ... SCR 1B10h DLL 1B12h DLH 1B18h PWREMU_MGMT Copyright © 2009–2010, Texas Instruments Incorporated Table 6-24. UART Registers REGISTER NAME Receiver Buffer Register (read only) Transmitter Holding Register (write only) Interrupt Enable Register Interrupt Identification Register (read only) FIFO Control Register (write only) ...

  • Page 96

    ... Peripheral Information and Electrical Specifications (1) CV (see Figure 6-24) CV MIN Start Bit Data Bits 5 4 Start Bit Data Bits Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com (see Figure 6-24 UNIT MIN MAX MIN MAX ...

  • Page 97

    ... I2S1RXLT0 2929h I2S1RXLT1 292Ch I2S1RXRT0 292Dh I2S1RXRT1 Copyright © 2009–2010, Texas Instruments Incorporated show the I2S0 through I2S3 registers. Table 6-27. I2S0 Registers REGISTER NAME I2S0 Serializer Control Register I2S0 Sample Rate Generator Register I2S0 Transmit Left Data 0 Register I2S0 Transmit Left Data 1 Register ...

  • Page 98

    ... I2S3 Interrupt Flag Register I2S3 Interrupt Mask Register I2S3 Receive Left Data 0 Register I2S3 Receive Left Data 1 Register I2S3 Receive Right Data 0 Register I2S3 Receive Right Data 1 Register Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com ...

  • Page 99

    ... I2S_CLK low (CLKPOL = 1) ( SYSCLK period in ns. For example, when running parts at 100 MHz, use ns. (2) Use whichever value is greater. (3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK). Copyright © 2009–2010, Texas Instruments Incorporated MASTER ...

  • Page 100

    ... MAX MIN MAX (1) (2) (1) ( – – – – t w(CLKH) – – t – – Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com (see Figure 6-25) SLAVE 1.3 V UNIT DD DD MIN MAX MIN MAX (1) (2) (1) ( ...

  • Page 101

    ... FSV Delay time, I2S_CLK high to I2S_FS valid dmax(CLKH- (CLKPOL = 1) FSV) ( SYSCLK period in ns. For example, when running parts at 100 MHz, use ns. (2) Use whichever value is greater. Copyright © 2009–2010, Texas Instruments Incorporated Figure MASTER MIN MAX MIN 40 or ...

  • Page 102

    ... Peripheral Information and Electrical Specifications [I/O = 1.8 V] (see Figure 6-25) MASTER MIN MAX MIN (1) 2P (1) ( Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com SLAVE = 1 1. 1.3 V UNIT DD DD MAX MIN MAX MIN MAX (1) 2P (1) ( ...

  • Page 103

    ... I2S_CLK (CLKPOL = 0) I2S_CLK (CLKPOL = 1) I2S_FS (Output, MODE = 1) I2S_FS (Input, MODE = 0) I2S_DX I2S_RX Copyright © 2009–2010, Texas Instruments Incorporated Figure 6-25. I2S Input and Output Timings Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 TMS320VC5505 SPRS503B – JUNE 2009 – REVISED JANUARY 2010 ...

  • Page 104

    ... LCD DMA Frame Buffer 1 Base Address Register 0 LCD DMA Frame Buffer 1 Base Address Register 1 LCD DMA Frame Buffer 1 Ceiling Address Register 0 LCD DMA Frame Buffer 1 Ceiling Address Register 1 Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 105

    ... LCD_EN_RDB low Delay time, LCD_CLK rising edge 14 t d(LCD_D_Z) to LCD_D[15:0] in 3-state Delay time, LCD_CLK rising edge 15 t d(Z_LCD_D) to LCD_D[15:0] valid from 3-state Copyright © 2009–2010, Texas Instruments Incorporated (1) (see Figure 6- 1. MIN MAX 25 0 Figure 6-26 through Figure ...

  • Page 106

    ... CS_DELA Y (1–5) (0- Read Data 13 12 Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 R_HOLD (1 to 15) CS_DELAY R_STROBE ( 63 Data[7:0] Read Status W_HOLD (1–15) W_SU W_STROBE CS_DELA Y (0–31) (1–63 Data[7:0] Write Instruction Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com ...

  • Page 107

    ... LCD_CLK [Internal] 4 LCD_D[15:0] Write Address 6 LCD_CSx_Ex (async mode) 8 LCD_RS 10 LCD_RW_WRB LCD_EN_RDB Figure 6-28. Micro-Interface Graphic Display 6800 Write Copyright © 2009–2010, Texas Instruments Incorporated W_HOLD (1-15) W_STROBE CS_DELA Y (1-63) (0- Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): ...

  • Page 108

    ... Figure 6-29. Micro-Interface Graphic Display 6800 Read 108 Peripheral Information and Electrical Specifications W_HOLD (1-15) W_STROBE CS_DELA Y (1-63) (0- Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com R_SU (0-31) R_STROBE R_HOLD CS_DELA Y (1-63 (1-15) (0- Data[15:0] Read Data Copyright © 2009–2010, Texas Instruments Incorporated CS0 CS1 RS R/W EN ...

  • Page 109

    ... R_SU (0-31) R_STROBE R_HOLD (1-63) LCD_CLK [Internal] 14 LCD_D[15:0] 6 LCD_CSx_Ex (Async Mode) LCD_RS LCD_RW_WRB LCD_EN_RDB Figure 6-30. Micro-Interface Graphic Display 6800 Status Copyright © 2009–2010, Texas Instruments Incorporated R_SU (0-31) CS_DELA Y (1-15) (0- Read 7 Data 12 13 Peripheral Information and Electrical Specifications ...

  • Page 110

    ... Figure 6-31. Micro-Interface Graphic Display 8080 Write 110 Peripheral Information and Electrical Specifications W_HOLD (1-15) W_STROBE CS_DELA Y (1-63) (0- Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com W_HOLD (1-15) W_SU W_STROBE CS_DELA Y (0-31) (1-63 DATA[15:0] Write Data Copyright © 2009–2010, Texas Instruments Incorporated CS0 CS1 RS WRB RDB ...

  • Page 111

    ... W_SU (0-31) LCD_CLK [Internal] 4 LCD_D[15:0] Write Address 6 LCD_CSx_Ex (async mode) 8 LCD_RS LCD_RW_WRB LCD_EN_RDB Figure 6-32. Micro-Interface Graphic Display 8080 Read Copyright © 2009–2010, Texas Instruments Incorporated W_HOLD R_SU (1-15) (0-31) W_STROBE CS_DELA Y (1-63) (0- Peripheral Information and Electrical Specifications Submit Documentation Feedback ...

  • Page 112

    ... Figure 6-33. Micro-Interface Graphic Display 8080 Status 112 Peripheral Information and Electrical Specifications R_SU (0-31) R_HOLD CS_DELA Y R_STROBE R_HOLD (1-15) (0- Read Data Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com CS_DELA Y (1-15) (1-63) (0- Data[15:0] Read Status 7 CS0 CS1 9 ...

  • Page 113

    ... Full-scale offset error set 8 Analog input impedance 9 Signal-to-noise ratio Copyright © 2009–2010, Texas Instruments Incorporated Table 6-38. SAR Analog Control Registers REGISTER DESCRIPTION SAR A/D Control Register SAR A/D Data Register SAR A/D Clock Control Register SAR A/D Reference and Pin Control Register ...

  • Page 114

    ... REGISTER NAME Clock Divider Register Clock Control Register Device Configuration Register 1 Device Configuration Register 2 Command Register 1 Command Register 2 Status Register 1 Status Register 2 Data Register 1 Data Register 2 Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 115

    ... Delay time, SPI_CS active to SPI_CLK active d(SPICS-SCLK) Output hold time, SPI_CS inactive to SPI_CLK 4 t oh(SCLKI-SPICSI) inactive ( the programable data delay in ns. Data delay can be programmed SPICLK clock cycles. Copyright © 2009–2010, Texas Instruments Incorporated Figure 6-34 (see Figure 6-34 through Figure CV MIN ...

  • Page 116

    ... Figure 6-37. SPI Mode 3 Transfer (CKPn = 1, CKPHn = 1) 116 Peripheral Information and Electrical Specifications Bn Bn Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 Bn-1 Bn-1 4 Bn-2 Bn-1 Bn-2 Bn Bn-1 Bn Bn-2 Bn-1 Bn-2 Bn-1 4 Copyright © 2009–2010, Texas Instruments Incorporated www.ti.com ...

  • Page 117

    ... INTMASKEDR1 (1) Before reading or writing to the USB registers, be sure to set the BYTEMODE bits to "00b" in the USB system control register to enable word accesses to the USB registers . Copyright © 2009–2010, Texas Instruments Incorporated REGISTER DESCRIPTION Revision Identification Register 1 Revision Identification Register 2 Control Register ...

  • Page 118

    ... Transmit and Receive FIFO Register 2 for Endpoint 1 Transmit and Receive FIFO Register 1 for Endpoint 2 Transmit and Receive FIFO Register 2 for Endpoint 2 Transmit and Receive FIFO Register 1 for Endpoint 3 Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www ...

  • Page 119

    ... RXCOUNT 8539h - 853Ch - 853Dh - Copyright © 2009–2010, Texas Instruments Incorporated REGISTER DESCRIPTION Transmit and Receive FIFO Register 2 for Endpoint 3 Transmit and Receive FIFO Register 1 for Endpoint 4 Transmit and Receive FIFO Register 2 for Endpoint 4 Dynamic FIFO Control Registers Reserved Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size (Index register set to ...

  • Page 120

    ... Receive Channel 3 Host Packet Configuration Register 1 A Receive Channel 3 Host Packet Configuration Register 2 A Receive Channel 3 Host Packet Configuration Register 1 B Receive Channel 3 Host Packet Configuration Register 2 B Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com (1) (continued) Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 121

    ... E804h + 16 × N QSTAT1B E805h + 16 × N QSTAT2B E808h + 16 × N QSTAT1C Copyright © 2009–2010, Texas Instruments Incorporated REGISTER DESCRIPTION CDMA Scheduler Control Register 1 CDMA Scheduler Control Register 1 CDMA Scheduler Table Word N Registers LSW ( 63) CDMA Scheduler Table Word N Registers MSW ( 63) Queue Manager (QMGR) Registers ...

  • Page 122

    ... Table 6-43. Universal Serial Bus (USB) Registers CPU WORD ACRONYM ADDRESS E809h + 16 × N QSTAT1C 122 Peripheral Information and Electrical Specifications REGISTER DESCRIPTION Queue Manager Queue N Status Register 63) Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com (1) (continued) ...

  • Page 123

    ... Full Speed and High Speed ( 100. [Excluding the first transaction from the Idle state.] RFM r f (4) Must accept as valid EOP USB_DM V CRS USB_DP Figure 6-38. USB2.0 Integrated Transceiver Interface Timing Copyright © 2009–2010, Texas Instruments Incorporated Figure 6-38) (2) (2) (3) (2) (4) ( per - jr 90 10% V ...

  • Page 124

    ... Watchdog Prescale Lock Register Watchdog Prescale Register REGISTER DESCRIPTION Timer 0 Control Register Timer 0 Period Register 1 Timer 0 Period Register 2 Timer 0 Counter Register 1 Timer 0 Counter Register 2 REGISTER DESCRIPTION Timer 1 Control Register Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 125

    ... TCR 1892h TIMPRD1 1893h TIMPRD2 1894h TIMCNT1 1895h TIMCNT2 Copyright © 2009–2010, Texas Instruments Incorporated REGISTER DESCRIPTION Timer 1 Period Register 1 Timer 1 Period Register 2 Timer 1 Counter Register 1 Timer 1 Counter Register 2 REGISTER DESCRIPTION Timer 2 Control Register Timer 2 Period Register 1 Timer 2 Period Register 2 ...

  • Page 126

    ... GPIO and how to configure them, see Functions and Section 4, Device Configuration of this document. 126 Peripheral Information and Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com Section ...

  • Page 127

    ... IOINTEDG2 1C0Eh IOINTEN1 1C0Fh IOINTEN2 1C10h IOINTFLG1 1C11h IOINTFLG2 Copyright © 2009–2010, Texas Instruments Incorporated Table 6-49. Table 6-49. GPIO Registers REGISTER NAME GPIO Direction Register 1 GPIO Direction Register 2 GPIO Data In Register 1 GPIO Data In Register 2 GPIO Data Out Register 1 ...

  • Page 128

    ... GP[x] Input (With IOINTEDGy = 1) GP[x] Output 128 Peripheral Information and Electrical Specifications (1) (see Figure 6-39) PARAMETER Figure 6-39. GPIO Port Timing Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com (see Figure 6-39 1. 1.3 V UNIT DD MIN ...

  • Page 129

    ... The pulse width given is sufficient to generate a CPU interrupt. However user wants to have VC5505 recognize the GP[x] input changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow device enough time to access the GPIO register through the internal bus. Copyright © 2009–2010, Texas Instruments Incorporated Polling GPIO_DIN register Polling GPIO_IFR register ...

  • Page 130

    ... JTAG controller is not connected to the JTAG pins. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations ...

  • Page 131

    ... Table 6-56. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port NO Delay time, TCK low to TDO valid d(TCKL-TDOV) 3 TCK TDO TDI TMS Copyright © 2009–2010, Texas Instruments Incorporated DESCRIPTION (see Figure 6-41) PARAMETER Figure 6-41. JTAG Test-Port Timing ...

  • Page 132

    ... This data is subject to change without notice and without revision of this document. 132 Mechanical Packaging and Orderable Information 1S0P 1S0P 2S2P 1S0P 2S2P Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 www.ti.com (1) °C/W AIR FLOW ...

  • Page 133

    PACKAGING INFORMATION (1) Orderable Device Status TMS320VC5505ZCH NRND (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is ...

  • Page 134

    ...

  • Page 135

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...