C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 208

• Manufacturer Part Number: C8051F330DK
• Description: DEV KIT FOR C8051F330/F331
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232
• Operating Supply Voltage: 7 V to 15 V
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F330
• Silicon Family Name: C8051F33x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F330, C8051F331
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1264

C8051F330/1/2/3/4/5
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Revision 1.3 to Revision 1.4
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Revision 1.4 to Revision 1.5
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Revision 1.5 to Revision 1.6
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Revision 1.6 to Revision 1.7
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212
OCUMENT
Removed references to C8051F330D throughout the data sheet because the 'F330D device is func-
tionally identical to the C8051F330 device (these two part numbers differ by package type only).
Updated titles of Chapters 5, 6, and 7 to show supported devices.
Updated Table 1.1, “Product Selection Guide,” on page 18.
- Added ordering part number information for lead-free parts.
Added Table 3.2, “Index to Electrical Characteristics Tables,” on page 34
Added Table 11.2, “Flash Security Summary,” on page 106 for clarity, replacing the Flash security sum-
maries text.
Updated Table 3.1 - Added supply current data from characterization.
Updated Table 5.1 - Added MIN/MAX numbers for ADC Offset and Full Scale Error.
Fixed SFR Definition 8.2 - Typo in bit descriptions - “2-0” changed to “3-0”.
Fixed SFR Definition 9.4 - Text at bottom of figure was cut off.
Added
Fixed
changed to “upper 7 bits”.
Fixed text in
or 3072 system clock cycles”.
Changed Table 19.4, Note 2 to refer to SYSCLK reset frequency = Internal Oscillator / 8.
Fixed Equation 19.6, “Watchdog Timer Offset in PCA Clocks,” - Typo in equation - “PCA0CPL4”
changed to “PCA0CPL2”.
Updated package drawings.
Removed PDIP package information.
Section “12. External RAM” on page 111
Section “11.4. Flash Write and Erase Guidelines” on page 107
Section “19.3.2. Watchdog Timer Usage” on page 203
C
HANGE
L
IST
Rev. 1.7
, paragraph 2 - Typo in description - “upper 6-bits”
to read “256 PCA clock cycles,
.