C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 98

• Manufacturer Part Number: C8051F330DK
• Description: DEV KIT FOR C8051F330/F331
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232
• Operating Supply Voltage: 7 V to 15 V
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F330
• Silicon Family Name: C8051F33x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F330, C8051F331
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1264

Note:
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Bit7
R
-
Do not use read-modify-write operations (ORL, ANL) on this register.
UNUSED. Read = 0. Write = don’t care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a FlashFlash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset
source.
1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source
(active-low).
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit. Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the V
monitor as a reset source. Note: writing ‘1’ to this bit before the V
and stabilized may cause a system reset. See register VDM0CN (SFR Definition 10.1)
0: Read: Last reset was not a power-on or V
reset source.
1: Read: Last reset was a power-on or V
indeterminate. Write: V
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
FERROR C0RSEF
Bit6
R
SFR Definition 10.2. RSTSRC: Reset Source
R/W
Bit5
DD
SWRSF
monitor is a reset source.
R/W
Bit4
WDTRSF MCDRSF
Rev. 1.7
Bit3
R
DD
monitor reset; all other reset flags 
DD
monitor reset. Write: V
R/W
Bit2
C8051F330/1/2/3/4/5
PORSF
R/W
Bit1
DD
SFR Address:
DD
PINRSF
monitor is enabled
Bit0
monitor is not a
R
0xEF
Reset Value
Variable
DD
101