C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 114

DEV KIT FOR F005/006/007

C8051F005DK

Manufacturer Part Number
C8051F005DK
Description
DEV KIT FOR F005/006/007
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F005DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F01x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F005
Silicon Family Name
C8051F00x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F005/006/007
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1188

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Figure 16.2 shows a typical SMBus configuration. The SMBus interface will work at any voltage between 3.0V
and 5.0V and different devices on the bus may operate at different voltage levels. The SCL (serial clock) and SDA
(serial data) lines are bi-directional. They must be connected to a positive power supply voltage through a pull-up
resistor or similar circuit. When the bus is free, both lines are pulled high. Every device connected to the bus must
have an open-drain or open-collector output for both the SCL and SDA lines. The maximum number of devices on
the bus is limited only by the requirement that the rise and fall times on the bus will not exceed 300ns and 1000ns,
respectively.
16.1.
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I
2. The I
3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum.
Supporting Documents
VDD = 5V
2
2
C-bus and how to use it (including specifications), Philips Semiconductor.
C-Bus Specification -- Version 2.0, Philips Semiconductor.
Figure 16.2. Typical SMBus Configuration
VDD = 3V
Master
Device
Rev. 1.7
Device 1
VDD = 5V
Slave
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Device 2
VDD = 3V
Slave
SDA
SCL
114

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