C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 130

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

18. UART
The UART is a serial port capable of asynchronous transmission. The UART can function in full duplex mode. In
all modes, receive data is buffered in a holding register. This allows the UART to start reception of a second
incoming data byte before software has finished reading the previous data byte.
The UART has an associated Serial Control Register (SCON) and a Serial Data Buffer (SBUF) in the SFRs. The
single SBUF location provides access to both transmit and receive registers. Reads access the Receive register and
writes access the Transmit register automatically.
The UART is capable of generating interrupts if enabled. The UART has two sources of interrupts: a Transmit
Interrupt flag, TI (SCON.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI
(SCON.0) set when reception of a data byte is complete. The UART interrupt flags are not cleared by hardware
when the CPU vectors to the interrupt service routine. They must be cleared manually by software. This allows
software to determine the cause of the UART interrupt (transmit complete or receive complete).
S
M
O
D
Overflow
Overflow
Timer 1
Timer 2
PCON
SYSCLK
2
M
S
0
Baud Rate Generation Logic
SMOD
1
0
S
M
1
S
M
2
SCON
R
E
N
32
64
12
T
B
8
R
B
8
T
I
SMOD
RCLK
TCLK
R
I
0
1
0
1
1
0
16
16
R
C
L
K
T2CON
Figure 18.1. UART Block Diagram
T
C
L
K
SFR Bus
00
01
10
11
00
01
10
11
SM0, SM1
{MODE}
Write to
SBUF
Rev. 1.7
Rx Clock
Tx Clock
Start
Start
Bit Detector
Interrupt
Serial
Port
D
TB8
SET
CLR
Stop Bit
Q
Gen.
SBUF
Read
TI
RI
Tx Control
Tx IRQ
Rx IRQ
Rx Control
Zero Detector
SFR Bus
Input Shift Register
SBUF
SBUF
Enable
REN
Shift
(9 bits)
0x1FF
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
RB8
MSB
Load SBUF
SBUF
Send
Data
Load
Shift
Shift
TX
RX
Crossbar
Crossbar
Port I/O
130