C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 132

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start
bit, eight data bits (LSB first), and one stop bit (see the timing diagram in Figure 18.4). Data are transmitted from
the TX pin and received at the RX pin (see the interconnection diagram in Figure 18.5). On receive, the eight data
bits are stored in SBUF and the stop bit goes into RB8 (SCON.2).
Data transmission begins when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt
Flag (SCON.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN Receive Enable bit (SCON.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF receive register if the following conditions are met: RI must be logic 0, and if SM2 is
logic 1, the stop bit must be logic 1.
If these conditions are met, the eight bits of data are stored in SBUF, the stop bit is stored in RB8, and the RI flag is
set. If these conditions are not met, SBUF and RB8 will not be loaded and the RI flag will not be set. An interrupt
will occur if enabled when either TI or RI is set.
The baud rate generated in Mode 1 is a function of timer overflow. The UART can use Timer 1 operating in 8-bit
Counter/Timer with Auto-Reload Mode, or Timer 2 operating in Baud Rate Generator Mode to generate the baud
rate (note that the TX and RX clock sources are selected separately). On each timer overflow event (a rollover from
all ones (0xFF for Timer 1, 0xFFFF for Timer 2) to zero), a clock is sent to the baud rate logic.
When Timer 1 is selected as a baud rate source, the SMOD bit (PCON.7) selects whether or not to divide the
Timer 1 overflow rate by two. On reset, the SMOD bit is logic 0, thus selecting the lower speed baud rate by
default. The SMOD bit affects the baud rate generated by Timer 1 as follows:
When Timer 2 is selected as a baud rate source, the baud rate generated by Timer 2 is as follows:
The Timer 1 overflow rate is determined by the Timer 1 clock source (T1CLK) and reload value (TH1). The
frequency of T1CLK can be selected as SYSCLK, SYSCLK/12, or an external clock source. The Timer 1 overflow
rate can be calculated as follows:
For example, assume TMOD = 0x20.
If T1M (CKCON.4) is logic 1, then the above equation becomes:
If T1M (CKCON.4) is logic 0, then the above equation becomes:
SPACE
MARK
BIT TIMES
BIT SAMPLING
Mode 1 Baud Rate = (1 / 32) * T1_OVERFLOWRATE (when the SMOD bit is set to logic 0).
Mode 1 Baud Rate = (1 / 16) * T1_OVERFLOWRATE (when the SMOD bit is set to logic 1).
START
BIT
Figure 18.4. UART Mode 1 Timing Diagram
Mode 1 Baud Rate = (1 / 16) * T2_OVERFLOWRATE.
D0
T1_OVERFLOWRATE = (SYSCLK/12) / (256 – TH1).
T1_OVERFLOWRATE = (SYSCLK) / (256 – TH1).
T1_OVERFLOWRATE = T1CLK / (256 – TH1).
D1
D2
Rev. 1.7
D3
D4
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
D5
D6
D7
STOP
BIT
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