C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 137

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

137
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Bits7-6: SM0-SM1: Serial Port Operation Mode.
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SM0
R/W
Bit7
These bits select the Serial Port Operation Mode.
The function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect
Mode 1: Checks for valid stop bit.
Mode 2 and 3: Multiprocessor Communications Enable.
This bit enables/disables the UART receiver.
0: UART reception disabled.
1: UART reception enabled.
TB8: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It
is not used in Modes 0 and 1. Set or cleared by software as required.
RB8: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if
SM2 is logic 0, RB8 is assigned the logic level of the received stop bit. RB8 is not used in
Mode 0.
Set by hardware when a byte of data has been transmitted by the UART (after the 8
Mode 0, or at the beginning of the stop bit in other modes). When the UART interrupt is
enabled, setting this bit causes the CPU to vector to the UART interrupt service routine.
This bit must be cleared manually by software
Set by hardware when a byte of data has been received by the UART (after the 8
Mode 0, or after the stop bit in other modes – see SM2 bit for exception). When the
UART interrupt is enabled, setting this bit causes the CPU to vector to the UART interrupt
service routine. This bit must be cleared manually by software.
SM2: Multiprocessor Communication Enable.
REN: Receive Enable.
TI: Transmit Interrupt Flag.
RI: Receive Interrupt Flag.
SM0
0
0
1
1
SM1
R/W
Bit6
0: Logic level of stop bit is ignored.
1: RI will only be activated if stop bit is logic level 1.
0: Logic level of ninth bit is ignored.
1: RI is set and an interrupt is generated only when the ninth bit is logic 1.
SM1
Figure 18.9. SCON: Serial Port Control Register
0
1
0
1
SM2
R/W
Bit5
Mode
Mode 0: Synchronous Mode
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 3: 9-Bit UART, Variable Baud Rate
REN
R/W
Bit4
Rev. 1.7
TB8
R/W
Bit3
RB8
R/W
Bit2
R/W
Bit1
TI
(bit addressable)
th
bit in
R/W
Bit0
th
RI
bit in
0x98
SFR Address:
Reset Value
00000000