C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 149

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

19.2.3. Mode 2: Baud Rate Generator
Timer 2 can be used as a baud rate generator for the serial port (UART) when the UART is operated in modes 1 or 3
(refer to Section 18.1 for more information on UART operational modes). In Baud Rate Generator mode, Timer 2
works similarly to the auto-reload mode. On overflow, the 16-bit value held in the two capture registers (RCAP2H,
RCAP2L) is automatically loaded into the counter/timer register. However, the TF2 overflow flag is not set and no
interrupt is generated. Instead, the overflow event is used as the input to the UART’s shift clock. Timer 2
overflows can be used to generate baud rates for transmit and/or receive independently.
The Baud Rate Generator mode is selected by setting RCLK (T2CON.5) and/or TCLK (T2CON.4) to logic one.
When RCLK or TCLK is set to logic 1, Timer 2 operates in the auto-reload mode regardless of the state of the
CP/RL2 bit. The baud rate for the UART, when operating in mode 1 or 3, is determined by the Timer 2 overflow
rate:
Note, in all other modes, the timebase for the timer is the system clock divided by one or twelve as selected by the
T2M bit in CKCON. However, in Baud Rate Generator mode, the timebase is the system clock divided by two. No
other divisor selection is possible. If a different time base is required, setting the C/T2 bit to logic 1 will allow the
timebase to be derived from the external input pin T2. In this case, the baud rate for the UART is calculated as:
Where FCLK is the frequency of the signal supplied to T2 and [RCAP2H:RCAP2L] is the 16-bit value held in the
capture registers.
As explained above, in Baud Rate Generator mode, Timer 2 does not set the TF2 overflow flag and therefore cannot
generate an interrupt. However, if EXEN2 is set to logic 1, a high-to-low transition on the T2EX input pin will set
the EXF2 flag and a Timer 2 interrupt will occur if enabled. Therefore, the T2EX input may be used as an
additional external interrupt source.
149
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Overflow
Timer 1
SYSCLK
T2EX
Baud Rate = Timer 2 Overflow Rate / 16.
Baud Rate = FCLK / [32 * (65536 – [RCAP2H:RCAP2L]) ]
T2
Crossbar
Crossbar
2
2
EXEN2
TR2
0
1
0
1
Figure 19.13. T2 Mode 2 Block Diagram
M
O
D
S
C/T2
PCON
G
F
1
G
F
0
S
O
P
T
D
L
E
I
TCLK
Rev. 1.7
CP/RL2
RCAP2L
EXEN2
RCLK
TCLK
EXF2
C/T2
TR2
TF2
TL2
RCAP2H
TH2
Interrupt
Reload
Timer 2
Overflow
1
0
1
0
TCLK
RCLK
16
16
RX Clock
TX Clock