C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 70

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

10.3.
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The
SFRs provide control and data exchange with the CIP-51’s resources and peripherals. The CIP-51 duplicates the
SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access
the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility
with the MCS-51™ instruction set. Table 10.3 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed any time the direct addressing mode is used to access memory locations from 0x80
to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well
as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are
reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the
corresponding pages of the datasheet, as indicated in Table 10.3, for a detailed description of each register.
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
* Refers to a register in the C8051F000/1/2/5/6/7 only.
** Refers to a register in the C8051F010/1/2/5/6/7 only.
*** Refers to a register in the C8051F005/06/07/15/16/17 only.
Address
D8
D0
A8
A0
F8
F0
E8
E0
C8
C0
B8
B0
98
90
88
80
0xBC
0xBE
0xC5
0xC4
0xBF
0xE0
0xE8
Bit Addressable
SPI0CN
B
ADC0CN
ACC
PCA0CN
PSW
T2CON
SMB0CN
IP
P3
IE
P2
SCON
P1
TCON
P0
SPECIAL FUNCTION REGISTERS
0(8)
Register
ACC
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
ADC0L
PCA0H
PCA0L
XBR0
PCA0MD
REF0CN
SMB0STA
OSCXCN
SBUF
TMR3CN
TMOD
SP
Table 10.2. Special Function Register Memory Map
1(9)
Description
Accumulator
ADC Configuration
ADC Control
ADC Greater-Than Data Word (High Byte)
ADC Greater-Than Data Word (Low Byte)
ADC Data Word (High Byte)
ADC Data Word (Low Byte)
Table 10.3. Special Function Registers
PCA0CPL0
XBR1
PCA0CPM0
SMB0DAT
SPI0CFG
TMR3RLL
TL0
DPL
PCA0CPH0
DAC0L
RCAP2L
AMX0CF
OSCICN
2(A)
PCA0CPH1
PCA0CPL1
XBR2
PCA0CPM1
DAC0H
RCAP2H
SMB0ADR
AMX0SL
SPI0DAT
TMR3RLH
TL1
DPH
Rev. 1.7
3(B)
PCA0CPH2
PCA0CPL2
PCA0CPM2
DAC0CN
TL2
ADC0GTL
ADC0CF
PRT0CF
TMR3L
TH0
4(C)
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PCA0CPH3
PCA0CPL3
PCA0CPM3
DAC1L
TH2
ADC0GTH
PRT1IF
PRT1CF
SPI0CKR
TMR3H
TH1
5(D)
PCA0CPH4
EIP1
PCA0CPL4
EIE1
PCA0CPM4
DAC1H
ADC0LTL
ADC0L
FLSCL
PRT2CF
CPT0CN
CKCON
6(E)
WDTCN
EIP2
RSTSRC
EIE2
DAC1CN
SMB0CR
ADC0LTH
ADC0H
FLACL***
EMI0CN***
PRT3CF
CPT1CN
PSCTL
PCON
Page No.
33*, 42**
34*, 45**
36*, 47**
36*, 47**
35*, 46**
35*, 46**
7(F)
76
70