C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 79

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

10.4.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet
section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the
peripheral and the behavior of its interrupt-pending flag(s).
79
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
EA
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask
settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
IEGF0: General Purpose Flag 0.
This is a general purpose flag for use under software control.
This bit sets the masking of the Timer 2 interrupt.
0: Disable all Timer 2 interrupts.
1: Enable interrupt requests generated by the TF2 flag (T2CON.7)
This bit sets the masking of the Serial Port (UART) interrupt.
0: Disable all UART interrupts.
1: Enable interrupt requests generated by the R1 flag (SCON.0) or T1 flag (SCON.1).
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupts.
1: Enable interrupt requests generated by the TF1 flag (TCON.7).
This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 pin.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupts.
1: Enable interrupt requests generated by the TF0 flag (TCON.5).
This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 pin.
EA: Enable All Interrupts.
ET2: Enable Timer 2 Interrupt.
ES: Enable Serial Port (UART) Interrupt.
ET1: Enable Timer 1 Interrupt.
EX1: Enable External Interrupt 1.
ET0: Enable Timer 0 Interrupt.
EX0: Enable External Interrupt 0.
IEGF0
R/W
Bit6
R/W
ET2
Bit5
Figure 10.9. IE: Interrupt Enable
R/W
Bit4
ES
Rev. 1.7
ET1
R/W
Bit3
EX1
R/W
Bit2
R/W
ET0
Bit1
(bit addressable)
EX0
R/W
Bit0
0xA8
SFR Address:
Reset Value
00000000