C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 126

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

C8051F020/1/2/3
126
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SMOD0
R/W
Bit7
SMOD0: UART0 Baud Rate Doubler Enable.
This bit enables/disables the divide-by-two function of the UART0 baud rate logic for configurations
described in the UART0 section.
0: UART0 baud rate divide-by-two enabled.
1: UART0 baud rate divide-by-two disabled.
SSTAT0: UART0 Enhanced Status Mode Select.
This bit controls the access mode of the SM20-SM00 bits in register SCON0.
0: Reads/writes of SM20-SM00 access the SM20-SM00 UART0 mode setting.
1: Reads/writes of SM20-SM00 access the Framing Error (FE0), RX Overrun (RXOV0), and TX
Collision (TXCOL0) status bits.
Reserved. Read is undefined. Must write 0.
SMOD1: UART1 Baud Rate Doubler Enable.
This bit enables/disables the divide-by-two function of the UART1 baud rate logic for configurations
described in the UART1 section.
0: UART1 baud rate divide-by-two enabled.
1: UART1 baud rate divide-by-two disabled.
SSTAT1: UART1 Enhanced Status Mode Select.
This bit controls the access mode of the SM21-SM01 bits in SCON1.
0: Reads/writes of SM21-SM01 access the SM21-SM01 UART1 mode setting.
1: Reads/writes of SM21-SM01 access the Framing Error (FE1), RX Overrun (RXOV1), and TX
Collision (TXCOL1) status bits.
Reserved. Read is undefined. Must write 0.
STOP: STOP Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’.
1: CIP-51 forced into power-down mode. (Turns off internal oscillator).
IDLE: IDLE Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’.
1: CIP-51 forced into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and all
peripherals remain active.)
SSTAT0
R/W
Bit6
Reserved
R/W
Bit5
Figure 12.15. PCON: Power Control
SMOD1
R/W
Bit4
SSTAT1
Rev. 1.4
R/W
Bit3
Reserved
R/W
Bit2
STOP
R/W
Bit1
IDLE
R/W
Bit0
SFR Address:
00000000
Reset Value
0x87