C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 175

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

Bits7-0:
Note:
Bits7-0:
Note:
Bits7-0:
Note:
P2.7
R/W
R/W
R/W
Bit7
Bit7
Bit7
P1MDOUT.[7:0]: Port1 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.
P2.[7:0]: Port2 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P2MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P2.n pin is logic low.
1: P2.n pin is logic high.
P2.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See
ORY INTERFACE AND ON-CHIP XRAM” on page 145
Memory Interface.
P2MDOUT.[7:0]: Port2 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.
P2.6
R/W
R/W
R/W
Bit6
Bit6
Bit6
Figure 17.14. P1MDOUT: Port1 Output Mode Register
Figure 17.16. P2MDOUT: Port2 Output Mode Register
P2.5
R/W
R/W
R/W
Bit5
Bit5
Bit5
Figure 17.15. P2: Port2 Data Register
P2.4
R/W
R/W
R/W
Bit4
Bit4
Bit4
P2.3
R/W
R/W
R/W
Bit3
Bit3
Bit3
Rev. 1.4
P2.2
R/W
R/W
R/W
Bit2
Bit2
Bit2
Section “16. EXTERNAL DATA MEM-
for more information about the External
P2.1
C8051F020/1/2/3
R/W
R/W
R/W
Bit1
Bit1
Bit1
(bit addressable)
P2.0
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
11111111
Reset Value
0xA5
0xA0
0xA6
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