C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 178

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

C8051F020/1/2/3
Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to assume a high-
impedance state. The Open-Drain configuration is useful to prevent contention between devices in systems where the
Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire.
The output modes of the Port pins on Ports 4 through 7 are determined by the bits in the P74OUT register (see
Figure 17.20). Each bit in P74OUT controls the output mode of a 4-bit bank of Port pins on Ports 4, 5, 6, and 7. A
logic 1 in P74OUT.7 will configure the output modes of 4 most-significant bits of Port 7, P7.[7:4], to Push-Pull; a
logic 0 in P74OUT.7 will configure the output modes of P7.[7:4] to Open-Drain.
17.2.3. Configuring Port Pins as Digital Inputs
A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the
associated bit in the Port Data register. For example, P7.7 is configured as a digital input by setting P74OUT.7 to a
logic 0 and P7.7 to a logic 1.
17.2.4. Weak Pull-ups
By default, each Port pin has an internal weak pull-up device enabled which provides a resistive connection (about
100 k) between the pin and VDD. The weak pull-up devices can be globally disabled by writing a logic 1 to the
Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically deactivated on any pin that is
driving a logic 0; that is, an output pin will not contend with its own pull-up device.
17.2.5. External Memory Interface
If the External Memory Interface (EMIF) is enabled on the High ports (Ports 4 through 7), EMIFLE (XBR2.1) should
be set to a logic 0.
If the External Memory Interface is enabled on the High ports and an off-chip MOVX operation occurs, the External
Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX
instruction, regardless of the settings of the Port Data registers. The output configuration of the Port pins is not
affected by the EMIF operation, except that Read operations will explicitly disable the output drivers on the Data Bus
during the MOVX execution. See
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP
XRAM” on page 145
for more information about the External Memory Interface.
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