C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 197

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

19.
The Serial Peripheral Interface (SPI0) provides access to a four-wire, full-duplex, serial bus. SPI0 may operate as a
master or a slave, and supports the connection of multiple slaves and masters on the same bus. A slave-select input
(NSS) is included in the SPI0 interface to select SPI0 as a slave; additional general purpose port I/O can be used as
slave-select outputs when SPI0 is operating as a master. Collision detection is provided when two or more masters
attempt a data transfer at the same time. When the SPI is configured as a master, the maximum data transfer rate (bits/
sec) is one-half the system clock frequency.
When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the
system clock frequency, provided that the master issues SCK, NSS, and the serial input data synchronously with the
system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer
rate (bits/sec) must be less that 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave
can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the
master issues SCK, NSS, and the serial input data synchronously with the system clock.
SERIAL PERIPHERAL INTERFACE BUS (SPI0)
SYSCLK
S
C
R
7
S
C
R
6
Clock Divide
SPI0CKR
S
C
R
5
SFR Bus
SPI0DAT
Write to
Logic
C
R
S
4
S
C
R
3
Data Path
Control
C
R
S
2
Receive Data Register
S
C
R
7
1
Figure 19.1. SPI Block Diagram
S
C
R
6
0
Shift Register
5
SPI CONTROL LOGIC
4
C
K
P
H
A
3
C
K
P
O
2
L
(Master Mode)
SFR Bus
SPI0CFG
SPI Clock
B
C
2
1
SPI0DAT
SPI0DAT
Read
Bit Count
B
C
0
1
Logic
C
B
0
F
R
S
2
Tx Data
R
F
S
1
Rx Data
F
R
S
0
Rev. 1.4
Pin Control
S
P
F
Control
I
Interface
Logic
Pin
W
O
C
L
M
O
D
F
SPI0CN
O
R
X
V
R
N
T
X
B
S
Y
MOSI
MISO
SCK
NSS
S
L
V
S
E
L
M
S
T
E
N
S
P
E
N
I
C
R
O
S
S
B
A
R
C8051F020/1/2/3
SPI IRQ
Port I/O
197